JPH08264765A - Power chip carrier and power semiconductor device using the same - Google Patents

Abstract

PURPOSE: To improve reliability, handling properties, manufacturing properties, and cooling efficiency, by metallographically joining the cathode electrode and the anode electrode of an MOS controlled power semiconductor element to a cathode side inner electrode and an anode side inner electrode. CONSTITUTION: A cathode electrode 303 and a collector electrode 304 of an Si substrate 301 are rigidly metallographically bonded to inner electrodes 307, 308. A gate electrode 309 arranged around an IGBT is connected with a gate terminal 311 through a wire. These are sealed with resin 313. The capacity of an IGBT is dependent also on the performance and the size of the Si substrate, and about 500-3000V and 50-300A. In the range of this capacity, application in this state is possible. Since the cathode electrode and the collector electrode of the IGBT are bonded to the inner electrodes 307, 308, heat can be made to escape from both sides. Thereby the thermal resistance and the reliability are improved and a wire bonding part is hardly deteriorated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS-controlled power semiconductor, and more particularly to a transistor (IGBT or the like) or a composite semiconductor (IGCT) of a transistor and a thyristor.
Etc.) and a diode, and a large-capacity semiconductor device which enables parallel operation by sandwiching and pressing these unit power chip carriers between the same metal substrates.

[0002]

2. Description of the Related Art In order to cope with higher performance and lower noise of power converters such as inverter devices, development of high-speed, low-loss switching elements is strongly desired. As this semiconductor element, an IGBT (Insulated Gate Bipolar)
Transistor) and IGCT (Insulated Gate Control)
led Thyristor). The IGBT is disclosed in, for example, the electronic technology August 1991 pp. As shown in 17-71, it is voltage driven, and high speed operation is possible. Furthermore, since it is voltage control, the conventional GTO that is a current control element is used.
Compared with a thyristor, the ON voltage can be lowered, so that the loss of the element can be reduced. Further, the IGCT can further reduce the on-voltage and increase the current as compared with the IGBT. However, since it is difficult to increase the chip area of a MOS control type semiconductor such as IGBT or IGCT from the viewpoint of process yield, it is indispensable to connect the chips in parallel when high power switching is performed. It is essential.

1A and 1B show a conventional single-sided cooling IG.
It is the figure which showed the plane and sectional structure of a BT module.
In the figure, 101 is an IGBT chip, 102 is a collector (anode) side supporting electrode plate, 103 is a bonding wire, 104 is an AlN substrate, 105 is a solder layer, 106 is an emitter electrode terminal, 107 is an Al electrode, and 108 is a gate electrode terminal. , 109 are collector (anode) electrode terminals and 1
Reference numeral 10 indicates a diode chip. The heat generated inside the IGBT chip 101 is dissipated to the outside through the collector side electrode terminal 109 which is a copper circuit plate, the AlN substrate 104 and the collector side electrode supporting plate 102 which is a metal substrate of Mo, copper or the like. As an example of such a single-sided cooling type IGBT module, for example, Mitsubishi Electric Technical Report vol 67, No. 9, 1993,
PP. 90-93.

On the other hand, the 1994 National Conference of the Institute of Electrical Engineers of Japan (N
FIG. 2 shows the IGBT of the pressure contact type package structure disclosed in O.507). This structure is IGBT chip 2
The characteristic is that the collector or anode side of No. 01 is bonded to the lower collector side electrode plate 203 by the bonding layer 202, and the pressing electrode 205 provided on the emitter is pressed and pressed by the emitter electrode plate 204 having the convex portion. . The gate electrode 206 is connected to the gate terminal 208 by the wire 207. Since it can be cooled from both sides, it has low thermal resistance and high reliability.

[0005]

In the conventional one-sided cooling type structure, since the cooling efficiency is low, the chip temperature rises when the IGBTs are mounted on the substrate at a high density, and the solder joint portion and the wire bonding portion are easily deteriorated. . In addition, the gate electrode (1
(Corresponding to the chip side electrode of 08) Since there is a fragile and thin gate oxide film immediately below, chip damage is likely to occur during wire bonding, which causes a problem in reliability of the joint portion. Further, in the case of the above structure, it is necessary to design the module structure each time in order to correspond to the series.

Further, in the pressure contact type package structure, since the emitter side has a pressure contact structure, the chip temperature rises when current is applied in a pressurized state. As a result, the pressurizing electrode extends more than the IGBT chip, so that an eccentric load is likely to occur and the contact resistance is likely to change. In addition, handling of dust, misalignment, etc. is likely to cause problems. Further, since the pressurizing electrode is provided on the chip, the ratio of closing the chip area of the MOS control unit becomes small, and the current capacity per area becomes small.

An object of the present invention is to provide a power chip carrier excellent in reliability, handleability, manufacturability and cooling efficiency.

Another object of the present invention is to provide a power semiconductor device which can be easily increased in capacity and series based on the power chip carrier.

[0009]

According to the chip carrier of the present invention, the cathode electrode and the anode electrode of the MOS control type power semiconductor element are metallurgically bonded to the cathode side inner electrode and the anode side inner electrode. .

According to an embodiment, the cathode electrode and the anode electrode have Al as the first layer and are bonded and the uppermost layer is composed of Ag or Au, and the intermediate layer has an adhesive layer composed of Cr, Ti or Ni. . The cathode-side internal electrode and the anode-side internal electrode have Ni as the first layer, and the uppermost layer to be bonded has an adhesive layer composed of Ag or Au. Further, the junction between the cathode electrode and the cathode-side internal electrode and the junction between the anode electrode and the anode-side internal electrode may be metallurgically joined by mutual diffusion of Ag and Ag or Ag and Au. preferable. This Ag and Ag,
Or, the metallurgical bonding by mutual diffusion of Ag and Au is 2
It is desirable to be performed at 50 ° C. or lower.

According to the power semiconductor device of the present invention, a plurality of the above-mentioned power chip carriers are used, and a plurality of insulating substrates are metallurgically bonded to the cathode side internal electrode and the anode side internal electrode of each of these power chip carriers. And an insulating substrate bonded to the cathode-side internal electrode, and
First pressure-connected to an insulating substrate bonded to an anode-side internal electrode to fix a plurality of power chip carriers in parallel
And a second external electrode.

A semiconductor device characterized in that it is desirable to have a sea surface metal layer or a super elastic alloy layer between the insulating substrate bonded to the cathode side internal electrode and the first external electrode.

[0013]

In the structure of the present invention, since the electrodes on the main surfaces of both the anode and cathode of the semiconductor element substrate are metallurgically bonded to the internal electrodes, compared to the pressure contact structure in which an air layer is interposed at the interface, Can be sufficiently cooled and has low thermal resistance. Further, the unbalanced load phenomenon peculiar to the pressure contact structure hardly occurs, and the handling property such as dust and misalignment is not deteriorated. For example, in the case of the IGBT module to which the present invention is applied, the pressure dependence of VCE (saturation voltage) becomes extremely small. That is, the pressing force can be reduced. From the above, the structure of the present invention is advantageous for miniaturization and high reliability. Further, since it is resin-sealed, it can be used in a state in which an insulating plate is not connected, that is, a unit module as it is depending on the application.

The metallurgical bonding of the present invention is preferably carried out at a temperature of 250 ° C. or less, but if the connection is made at a temperature of around 120 to 150 ° C., the internal electrodes will be W, Mo or Cu--Al.
Not only materials having a low coefficient of thermal expansion such as N, Cu-SiC, Cu-W, and Cu-Mo but also materials having a relatively large coefficient of thermal expansion such as Cu and Al can be used. Since the temperature is low, the thermal stress generated in the joint can be reduced even if the mismatch of the thermal expansion coefficient is large.

In the power semiconductor device of the present invention, the above-described power chip carrier is used as a module unit and connected in parallel.

That is, in the case of a MOS control type semiconductor, since it is difficult to make the chip 3 cm square or more from the viewpoint of chip yield, the chip capacity is at most about 100 amperes, which is increased to several thousand amperes. Therefore, it is necessary to operate many chips at the same time. Therefore,
The conventional one-sided cooling type module has a considerably large size in consideration of cooling efficiency. Further, it is necessary to design the chip position, the terminal position, etc. according to the capacity and to evaluate the reliability of the manufactured module, which makes it difficult to make a series.

According to the power semiconductor device of the present invention, the above-described small-sized power chip carrier with high cooling efficiency and high reliability is used, and each power chip carrier has the first and second external parts. The electrodes are connected in parallel. Therefore, a large-capacity power semiconductor device that can be easily made into a series, is small, and is highly reliable can be realized.

Further, since the sea surface metal layer or the super elastic alloy layer is provided between the insulating substrate joined to the cathode side internal electrode and the first external electrode, each power chip carrier is uniformly pressed. Therefore, reliability is further increased.

[0019]

EXAMPLES The present invention will be specifically described below with reference to examples.

3 (a) and 3 (b) show an example of a sectional structure of the power chip carrier of the present invention. Further, FIG. 4 shows a sectional view of an IGBT used for a power chip carrier. In FIG. 3, 301 is a Si substrate, 302 is a gate, 30
3 is a cathode electrode, 304 is a collector (anode) side electrode, 305 is a cathode side adhesive layer, 306 is a collector (anode) side adhesive layer, 307 is a cathode side internal electrode, 30
8 is a collector (anode) side internal electrode, 309 is a gate electrode, 310 is a bonding wire, 311 is a gate terminal, 312 is an insulating support substrate, 313 is a resin, 314 is an adhesive layer with the cathode side insulating substrate, and 315 is a collector ( Adhesive layers to the (anode) side insulating plate, 316 and 317 are insulating substrates. The feature of FIG. 3A is that the cathode electrode 303 and the collector (anode) electrode 304 of the Si substrate 301 and the internal electrodes 307 and 308 are strongly metallurgically adhered to each other.
The gate electrode 309 arranged around the GBT is connected to the gate terminal 311 by a wire and is sealed with the resin 313. The gate electrode 309 is connected to the gate electrode 302 located between the emitter electrodes 405 in FIG. Note that 406 in FIG. 4 is an insulating film that insulates the cathode electrode 303 from the gate 302.

In this structure, the capacity of the IGBT depends on the performance and size of the Si substrate, but it is 500 to 30.
00V, about 50 to 300 A, and within this capacity range, it can be used in this state. Further, since the cathode and collector electrodes of the IGBT are bonded to the internal electrodes 307 and 308, heat can be dissipated from both sides (double-sided cooling), which is extremely advantageous in terms of thermal resistance and reliability as compared with the prior art. . Therefore, the wire bonding part is also less likely to deteriorate.

Cathode electrode 303, collector electrode 304
The electrode structure of Al / Cr / Ni / Ag, Al / N
i / Ti / Ni / Au or Al / Cr / Ag, Al
/ Ni / Au, Al / Cr / Ag, etc. as the first layer,
The uppermost layer is Ag or Au, and C, which improves adhesion, is in the middle.
It only has to be composed of an r layer, a Ti layer and a Ni layer which is a barrier. On the other hand, the adhesive layer of the internal electrodes 307 and 308 is Ni /
It consists of Ag. Metal bonding at a temperature of 250 ° C. or lower is completed by the mutual diffusion of Ag and Ag or Au.

On the other hand, in the single-sided cooling type shown in FIG. 1, in the case of the solder connection 105, the back surface of the IGBT chip is Al / Cr / Ni / Ag treated, but on the emitter electrode plate 106. Ni plating is applied to Pb-S
It is connected with n or Sn-Sb solder. In this case, Ag diffuses into the solder, Ni and Sn compounds are generated at the interfaces on both sides, and the adhesion is completed. The compound of Ni and Sn does not grow sufficiently unless the temperature reaches 250 ° C or higher.
Similarly, the solder connection between the AlN substrate 102 and the substrate 104 is N
A compound of i and Sn is produced to complete the joining. The formation of the compound of Ni and Sn is considerably affected not only by the bonding temperature but also by the oxide film (NiO, Ni ₂ O ₃ ) on the surface of the Ni plating film, dirt and gas in the solder, and a large void is generated at the interface and in the solder. There is a large variation in bonding due to defects such as.

In this embodiment, internal electrodes and Ag on the insulating substrate are used.
Alternatively, low-temperature diffusion bonding with the Au and Ag films on the cathode and anode electrodes is possible only by setting the carbon concentration in the Au film to 30 at% or less. Carbon hinders diffusion bonding. When fine particles of Ag are used to reduce the carbon concentration to 30 at% or less, the internal electrode or the insulating substrate coated with Ag particles for removing carbon from the organic solvent is not used.
It may be heated in the air to a temperature of 50 ° C. When the Au or Ag film is formed by vapor deposition or sputtering, carbon can be eliminated, so that heat treatment is unnecessary.

In the structure shown in FIG. 3B, the insulating substrates 316 and 317 have internal electrodes 307 in order to connect a large number of chip carriers shown in FIG. 3A in parallel for the purpose of further increasing the capacity. , 308 and a connection layer 314 made of Ag.
Similarly, low temperature bonding is performed by 315. The gate electrode 309 is arranged around the IGBT substrate 301, and has a structure in which the oxide film of the gate 302 is less likely to be damaged during wire bonding. In addition to the wire, the thin plate may be used to connect the gate electrode and the external terminal. In this case, it is preferable to bond the anode and the cathode electrode by a method similar to the low temperature bonding.

In FIG. 3 (c), an Ag film is formed on the Mo internal electrode by powder or sputtering through a Ni plating film, and the Ag internal film is laminated by the same method as the Mo internal electrode.
The relationship between the bonding strength ratio and the carbon concentration in the Ag film of the sample bonded by heating to 00 ° C. in the atmosphere is shown. Ag is 30a
It can be seen that the bonding strength is remarkably reduced when t% or more.

FIG. 5 shows the structure of an IGBT in which a refractory metal such as TIW or TiN or a nitride layer 506 is provided between the gate 502 and the cathode electrode 503 in FIG. In the figure, 505 is an emitter electrode and 507 is a gate oxide. By using the IGBT substrate having the structure shown in FIG.
The power chip carrier shown in (a) and (b) can be manufactured in the same manner. Since the refractory metal compound layer 506 having high strength is present above the gate 502, the gate oxide 507 is exposed to external stress. Protected against, and improved reliability.

FIG. 6 shows a sectional view of a unit module using the IGBT chips shown in FIGS. 4 and 5, that is, a power chip carrier. This structure is characterized by the emitter electrode 614 and the cathode side internal electrode 6 as shown in FIG.
This is that the convex portion 07 is solid-phase bonded with the adhesive layer 605, and the internal electrode is not bonded to the cathode electrode 603 on the gate 602. Since the internal electrode 607 is directly connected to the emitter electrode 614 which serves as a heat sink for heat,
The cooling efficiency of heat is improved as compared with the case where the cathode 603 on the gate 602 is connected. Others are the same as the structure shown in FIG.

FIG. 6B shows an insulating substrate 617 for connecting a large number of FIG. 6A in parallel in order to further increase the capacity.
618 and the internal electrodes 607 and 608 to connect the connection layers 615 and 6
16 shows a structure in which low temperature metal bonding is performed.

In the above examples, the adhesive layer is made of an Ag layer, and the density thereof is preferably in the range of 60 to 100% as described later from the viewpoint of electric conductivity and stress relaxation.
This density changes depending on the size of Ag particles used and the bonding temperature. Also, as the internal electrodes 607 and 608,
When a material having a low coefficient of thermal expansion such as Mo or W is used, it is heated to a temperature of 200 ° C. or higher and the density of the bonding layer is 1
It may be close to 00%. On the other hand, the internal electrodes 607, 60
8 as Cu, Al and these and W, Mo, AlN, S
When using a composite material with a material having a low coefficient of thermal expansion such as iC, it is desirable to join at a low temperature of 200 ° C. or less from the viewpoint of ensuring reliability.

Although the embodiment of the structure of the power chip carrier using the IGBT substrate has been described above, the present invention can be applied not only to the MOS control type transistor but also to the MOS control type thyristor.

FIG. 7 shows a sectional structure of a MOS control type thyristor (IGCT) used in the power chip carrier of the present invention.
In the figure, 701 is an IGCT, 702 is a gate oxide film, 703 is a poly-Si gate, 704 is an insulating film on a thyristor, 705 is a cathode, and 706 is an anode side Al /
The Cr / Ni / Ag film and 707 are emitter electrodes. The insulating film 704 on the thyristor is, for example, PSG (Ph
ospo-Silicate-Glass) or SiO ₂ .

In the IGBT shown in FIG. 4, the emitter electrode 4
A smaller ratio of the length of the cathode electrode 403 on the gate to the length of 05 is more effective in increasing the withstand voltage and reducing the ON voltage, whereas in the IGCT, the length of the emitter electrode 707 in FIG. 7 is smaller. Is effective for increasing the withstand voltage and reducing the ON voltage. That is, since the bonding area with the cathode-side internal electrode can be increased, it can be said that the device is suitable for the power chip carrier in terms of reliability of the bonding portion and cooling efficiency.

FIG. 8 shows a sectional view of a power chip carrier manufactured by using the IGCT shown in FIG. Figure 8 (a)
Indicates the case of using in the capacity range of several hundred A. In the figure, 801 is an IGCT substrate, 802 is a gate insulating film, 803 is a gate, 804 is an insulating film, 805 is a cathode electrode, 806 is an emitter electrode, 807 is a collector side electrode, 808 is a cathode side adhesive layer, and 809 is a collector side. An adhesive layer, 810 is a cathode side internal electrode, 811 is a collector side internal electrode, 812 is a gate electrode, 813 is a bonding wire, 814 is a resin, and 815 is an insulating support substrate. The cathode electrode 805 and the collector electrode 807 are made of Al.
/ Cr / Ni / Ag, Al / Cr / Ag and Al / Cr
/ Ag. The bonding layers 808 and 809 on the cathode side internal electrode 810 and the collector side internal electrode 811 are made of Ag. The cathode electrode film 805 and the cathode-side internal electrode 810, and the collector-side electrode 807 and the collector-side internal electrode 811 are bonded to each other at a low temperature by diffusion of Ag. IGCT base 801 itself is ON
In addition to the low voltage, the cathode electrode 805 has a large area, so that a power chip carrier having particularly excellent cooling efficiency and reliability can be obtained. The gate electrode 812 is connected to the gate terminal 816 by wire bonding 813. In FIG. 8B, the internal electrodes 810 and 811 are further joined to the insulating plates 819 and 820.

In FIG. 9, two chip carriers 901 are arranged side by side, cathode internal electrodes 902 are connected to each other 903, collector electrodes 904 are connected to each other 905, gate electrodes 906 are connected to each other 907, and cooling fins 9 are provided from above and below the insulating plate 908.
10 shows a structure for use by increasing the capacity by sandwiching it with the external electrode 909 with 10 and tightening with a screw 911, pressurizing, and operating in parallel. In the figure, in order to uniformly pressurize the two chip carriers, between the cathode side insulator plate 908 and the cooling fin-equipped external electrode 909,
A spongy metal or superelastic alloy plate 912 is provided. This embodiment is a case of two power chip carriers, but by increasing the number of carriers, a semiconductor device that can handle a large amount of power becomes possible, and thus series formation is facilitated depending on the application.

Next, a method of manufacturing the power chip carrier will be described. Plating on the internal electrodes shown in FIG. 3 and FIG.
A Ni layer is provided by a technique such as sputtering or vapor deposition, and an ultrafine particle of Ag (100
(Less than 0Å) is evenly applied. Next, 3 in the atmosphere
C is removed by heating to a temperature of 00 ° C. or higher. In the next step, the same heating is performed in vacuum to remove the oxide film on the Ag surface. Next, the Ag layer on the electrodes of the IGBT and IGCT and the Ag layer on the surface of the internal electrode are overlapped, and heated to a temperature range of 150 to 250 degrees to bond them. Similarly when connecting to an insulating plate
g layer, wire bonding and resin sealing to complete. When a sputtered Ag or Au film is used in addition to the Ag fine particles described above, N on the internal electrode such as Mo is used.
An Ag film having a thickness of 2 to 20 μm is formed on the i film by a sputtering method in a temperature range of room temperature to 100 ° C. Subsequently, the anode and cathode electrodes of the MOS power semiconductor are overlapped and heated at a temperature of 100 to 250 ° C. in N ₂ in the air and bonded.

[0037]

According to the present invention, it is possible to provide a highly reliable, low thermal resistance, large capacity power chip carrier and a semiconductor device.

[Brief description of drawings]

FIG. 1 is a diagram showing a structure of a conventional single-sided cooling type semiconductor module.

FIG. 2 is a view showing a conventional pressure contact type double-sided cooling type module structure.

FIG. 3 is a diagram showing a power chip carrier of the present invention.

FIG. 4 is an IG used in the power chip carrier of the present invention.
It is a figure which shows the cross section of BT.

FIG. 5 is an IG used in the power chip carrier of the present invention.
It is sectional drawing of BT.

FIG. 6 is a diagram showing a power chip carrier of the present invention.

FIG. 7 is an IG used in the power chip carrier of the present invention.
It is sectional drawing of CT.

FIG. 8 is a sectional view showing a power chip carrier of the present invention.

FIG. 9 is a diagram showing a cross-sectional structure of a large-volume semiconductor of the present invention.

[Explanation of symbols]

301 ... Si substrate, 302 ... Gate, 303 ... Cathode electrode, 304 ... Collector (anode) side electrode, 305 ...
Cathode side adhesive layer, 306 ... Collector (anode) side adhesive layer, 307 ... Cathode side internal electrode, 308 ... Collector (anode) side internal electrode, 309 ... Gate electrode, 310
... Bonding wire, 311 ... Gate terminal, 312 ...
Insulating support substrate, 313 ... Resin, 314 ... Adhesive layer with cathode side insulating substrate, 315 ... Adhesive layer with collector (anode) side insulating plate, 316, 317 ... Insulating substrate.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Mitsuo Sato 7-1-1, Omika-cho, Hitachi-shi, Ibaraki Hitachi, Ltd. Hitachi Research Laboratory (72) Inventor, Hitoshi Yamada 7-chome, Omika-cho, Hitachi-shi, Ibaraki No. 1-1 Hitachi Ltd. Hitachi Research Laboratory (72) Inventor Hideo Kobayashi 7-11 Omika-cho, Hitachi-shi, Ibaraki Hitachi Incorporated Hitachi Research Laboratory (72) Inventor Hiroshi Nagase Hitachi City, Ibaraki Prefecture 7-1, Omika-cho, Hitachi Research Laboratory, Hitachi Ltd. (72) Inventor, Masateru Suwa 7-1, 1-1, Omika-cho, Hitachi City, Ibaraki Prefecture Hitachi Research Laboratory, Hitachi Ltd.

Claims (16)

[Claims] 1. An MO formed on one main surface of a semiconductor substrate.
An S-controlled power semiconductor element, a cathode electrode of the semiconductor element formed on one main surface of the semiconductor substrate, and the cathode electrode formed on one main surface of the semiconductor substrate via an insulating layer. A gate electrode of a semiconductor element, an anode electrode of the semiconductor element formed on the other main surface of the semiconductor substrate, a cathode-side internal electrode metallurgically bonded to the cathode electrode, the anode electrode and a metal A power chip carrier having an anode-side internal electrode that is logically joined. 2. The cathode electrode and the anode electrode according to claim 1, wherein Al is used as a first layer, and the uppermost layer is joined to A.
A power chip carrier, characterized in that it is made of g or Au, and the intermediate layer has an adhesive layer made of Cr, Ti or Ni. 3. The cathode-side internal electrode and the anode-side internal electrode according to claim 2, wherein Ni is a first layer, and an uppermost layer to be bonded has an adhesive layer composed of Ag or Au. Power chip carrier. 4. The method according to claim 3, wherein the cathode electrode and the cathode-side internal electrode are joined to each other and the anode electrode and the anode-side internal electrode are joined to each other by Ag and Ag or Ag.
A power chip carrier, which is metallurgically bonded by mutual diffusion of Au and Au. 5. The metallurgical bond according to claim 4, wherein the metallurgical bonding is 25 due to the mutual diffusion of Ag and Ag or Ag and Au.
A power chip carrier, which is performed at 0 ° C. or lower. 6. The cathode-side internal electrode and the anode-side internal electrode according to claim 5, wherein Mo or W, or A
A power chip carrier made of a composite material of 1, Cu and W, Mo, AlN or SiC. 7. The power chip carrier according to claim 1, wherein the cathode electrode is disposed on the gate electrode via an insulating layer. 8. The power chip carrier according to claim 7, wherein a layer of TiW, TiN, or nitride is formed on the gate electrode. 9. The power chip carrier according to claim 7, wherein the cathode-side internal electrode has a convex portion in the cathode electrode direction and is not in contact with the gate electrode. 10. A power chip carrier according to claim 1, wherein the power chip carrier is resin-sealed. 11. An M formed on one main surface of a semiconductor substrate.
The OS-controlled power semiconductor element, the cathode electrode of the semiconductor element formed on one main surface of the semiconductor substrate, and the cathode formed on one main surface of the semiconductor substrate via an insulating layer. A gate electrode of the semiconductor element, an anode electrode of the semiconductor element formed on the other main surface of the semiconductor substrate, a cathode-side internal electrode metallurgically bonded to the cathode electrode, and the anode electrode A plurality of power chip carriers having a metallurgically bonded anode-side internal electrode, and a plurality of insulating substrates metallurgically bonded to the cathode-side internal electrode and the anode-side internal electrode of each of the power chip carriers, An insulating substrate joined to the cathode-side internal electrode, and
A power semiconductor device comprising: a first and a second external electrode, which are pressure-connected to an insulating substrate bonded to the anode-side internal electrode and fix the plurality of power chip carriers in parallel. 12. The power semiconductor device according to claim 11, further comprising a sea surface metal layer or a super elastic alloy layer between the insulating substrate bonded to the cathode side internal electrode and the first external electrode. 13. A bonding layer containing Ag or Au as a main component between the cathode-side internal electrode and the insulating substrate and between the anode-side internal electrode and the insulating substrate according to claim 11. Power semiconductor device. 14. The cathode electrode and the anode electrode according to claim 11, 12 or 13, wherein Al is used as the first layer, and the uppermost layer is joined and composed of Ag or Au, and the intermediate layer is Cr, Ti or Ni. A power semiconductor device having an adhesive layer composed of: 15. The cathode-side internal electrode and the anode-side internal electrode according to claim 14, wherein Ni is the first layer, and the uppermost layer to be bonded has an adhesive layer composed of Ag or Au. Power semiconductor device. 16. The method according to claim 15, wherein the cathode electrode and the cathode-side internal electrode are joined to each other and the anode electrode and the anode-side internal electrode are joined to each other by Ag and Ag, or
A power semiconductor device characterized by being metallurgically bonded by mutual diffusion of Ag and Au.