JPH01147544U - - Google Patents
Info
- Publication number
- JPH01147544U JPH01147544U JP4205888U JP4205888U JPH01147544U JP H01147544 U JPH01147544 U JP H01147544U JP 4205888 U JP4205888 U JP 4205888U JP 4205888 U JP4205888 U JP 4205888U JP H01147544 U JPH01147544 U JP H01147544U
- Authority
- JP
- Japan
- Prior art keywords
- start bit
- data
- clock
- lsb
- serial digital
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Dc Digital Transmission (AREA)
- Communication Control (AREA)
Description
第１図は本考案のデータ受信回路の実施例を示
すブロツク図、第２図は第１図の各部波形を示す
タイミングチヤート、第３図は第１図のシフトレ
ジスタの状態を示す図、第４図は従来のデータ受
信回路を示すブロツク図、第５図は第４図の各部
波形を示すタイミングチヤート。
６……シフトレジスタ、７……ラツチ回路、１
２……クロツク発生回路、１３……パリテイチエ
ツク回路、１４……ラツチパルス発生回路。
FIG. 1 is a block diagram showing an embodiment of the data receiving circuit of the present invention, FIG. 2 is a timing chart showing waveforms of each part in FIG. 1, FIG. 3 is a diagram showing the state of the shift register in FIG. FIG. 4 is a block diagram showing a conventional data receiving circuit, and FIG. 5 is a timing chart showing waveforms of various parts in FIG. 6...Shift register, 7...Latch circuit, 1
2... Clock generation circuit, 13... Parity check circuit, 14... Latch pulse generation circuit.
Claims (1)
データを受信するデータ受信回路において、 リセツト信号により駆動されると共に前記スタ
ートビツトにより初期化され再駆動されるクロツ
ク発生回路と、 少なく共前記スタートビツトとシリアルデジタ
ルデータのビツト数を有し初期化状態において前
記スタートビツトのデータ極性と逆極性のデータ
がセツトされ前記クロツク発生回路からのクロツ
クによりＭＳＢからＬＳＢまで順次前記スタート
ビツト及びシリアルデジタルデータを入力するシ
フトレジスタと、 該シフトレジスタの出力をラツチするラツチ回
路とを備え、 前記シフトレジスタのＭＳＢにスタートビツト
がセツトされ前記クロツクにより該スタートビツ
トがＬＳＢにシフトされたことを検出し、このＭ
ＳＢからＬＳＢまでの期間中にシフトレジスタに
入力されるデータを前記シリアルデジタルデータ
として検出するようにした、 ことを特徴とするデータ受信回路。[Claims for Utility Model Registration] A data receiving circuit that receives serial digital data starting from a start bit, comprising: a clock generating circuit driven by a reset signal and initialized and re-driven by the start bit; It has a start bit and the number of bits of serial digital data, and in the initialization state, data of opposite polarity to the data polarity of the start bit is set, and the start bit and serial digital data are sequentially generated from MSB to LSB by the clock from the clock generation circuit. and a latch circuit that latches the output of the shift register, detects that a start bit is set in the MSB of the shift register and is shifted to the LSB by the clock, and detects that the start bit is shifted to the LSB by the clock. M
A data receiving circuit characterized in that data input to a shift register during a period from SB to LSB is detected as the serial digital data.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988042058U JPH0546365Y2 (en) | 1988-03-31 | 1988-03-31 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988042058U JPH0546365Y2 (en) | 1988-03-31 | 1988-03-31 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01147544U true JPH01147544U (en) | 1989-10-12 |
| JPH0546365Y2 JPH0546365Y2 (en) | 1993-12-03 |
Family
ID=31268483
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988042058U Expired - Lifetime JPH0546365Y2 (en) | 1988-03-31 | 1988-03-31 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0546365Y2 (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59216232A (en) * | 1983-05-24 | 1984-12-06 | Nec Corp | Information processing device |
-
1988
- 1988-03-31 JP JP1988042058U patent/JPH0546365Y2/ja not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59216232A (en) * | 1983-05-24 | 1984-12-06 | Nec Corp | Information processing device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0546365Y2 (en) | 1993-12-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| SE8103262L (en) | waveform generator | |
| JPH01147544U (en) | ||
| JPH01108629U (en) | ||
| JPS60237714A (en) | Digital signal generating device | |
| JPH01159424U (en) | ||
| JPH02840U (en) | ||
| JPH01147441U (en) | ||
| JPS6030641U (en) | Error correction device for parallel digital data | |
| JPH0357630U (en) | ||
| JPS5980751U (en) | Frequency/voltage converter for injection speed display | |
| JPH0322431U (en) | ||
| JPS62300U (en) | ||
| JPH0386682U (en) | ||
| JPH032280U (en) | ||
| JPH0231748U (en) | ||
| JPS60158250U (en) | data output device | |
| JPS62201844U (en) | ||
| JPS6183372U (en) | ||
| JPS6374829U (en) | ||
| JPH0286247U (en) | ||
| JPS63163075U (en) | ||
| JPS59127357U (en) | M code data code conversion circuit | |
| JPS6040136U (en) | Digital pulse width conversion circuit | |
| JPH03111199U (en) | ||
| JPS62183233U (en) |