JPH01143519U - - Google Patents
Info
- Publication number
- JPH01143519U JPH01143519U JP2421489U JP2421489U JPH01143519U JP H01143519 U JPH01143519 U JP H01143519U JP 2421489 U JP2421489 U JP 2421489U JP 2421489 U JP2421489 U JP 2421489U JP H01143519 U JPH01143519 U JP H01143519U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- sawtooth wave
- peak value
- generates
- input pulse
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000010354 integration Effects 0.000 claims description 3
- 230000000737 periodic effect Effects 0.000 claims description 2
- 238000000605 extraction Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Television Signal Processing For Recording (AREA)
- Manipulation Of Pulses (AREA)
Description
第１図は外乱を含む周期性パルスの一例の波形
図、第２図は本考案の一例の系統図、第３図はそ
の説明のための波形図、第４図、第５図は他の例
の系統図である。
１１は入力端子、１２，１３は単安定マルチバ
イブレータ、１４は鋸歯状波形成回路、１５はサ
ンプルホールド回路、１６は積分回路、１７はウ
インドコンパレータ、１８はゲート回路、１９，
２０は出力端子である。
Fig. 1 is a waveform diagram of an example of a periodic pulse containing disturbance, Fig. 2 is a system diagram of an example of the present invention, Fig. 3 is a waveform diagram for explaining it, and Figs. FIG. 2 is an example system diagram. 11 is an input terminal, 12 and 13 are monostable multivibrators, 14 is a sawtooth wave forming circuit, 15 is a sample hold circuit, 16 is an integration circuit, 17 is a window comparator, 18 is a gate circuit, 19,
20 is an output terminal.
Claims (1)
波発生回路と、上記鋸歯状波のピーク値をホール
ドするサンプルホールド回路と、上記ホールドさ
れた鋸歯状波のピーク値を平均化する積分回路と
、上記積分回路の出力信号と上記ピーク値により
上記入力パルス信号を取出す信号を発生するウイ
ンドコンパレータ回路とを具備して成る周期性パ
ルス抽出回路。 a sawtooth wave generation circuit that generates a sawtooth wave from an input pulse signal, a sample hold circuit that holds the peak value of the sawtooth wave, and an integration circuit that averages the peak value of the held sawtooth wave; A periodic pulse extraction circuit comprising a window comparator circuit that generates a signal for extracting the input pulse signal based on the output signal of the integration circuit and the peak value.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989024214U JPH0441628Y2 (en) | 1989-03-02 | 1989-03-02 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989024214U JPH0441628Y2 (en) | 1989-03-02 | 1989-03-02 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01143519U true JPH01143519U (en) | 1989-10-02 |
| JPH0441628Y2 JPH0441628Y2 (en) | 1992-09-30 |
Family
ID=31243875
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1989024214U Expired JPH0441628Y2 (en) | 1989-03-02 | 1989-03-02 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0441628Y2 (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS508918A (en) * | 1973-05-31 | 1975-01-29 |
-
1989
- 1989-03-02 JP JP1989024214U patent/JPH0441628Y2/ja not_active Expired
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS508918A (en) * | 1973-05-31 | 1975-01-29 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0441628Y2 (en) | 1992-09-30 |
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