JPH01142472A - Contactor for inspecting semiconductor device - Google Patents
Contactor for inspecting semiconductor deviceInfo
- Publication number
- JPH01142472A JPH01142472A JP30182987A JP30182987A JPH01142472A JP H01142472 A JPH01142472 A JP H01142472A JP 30182987 A JP30182987 A JP 30182987A JP 30182987 A JP30182987 A JP 30182987A JP H01142472 A JPH01142472 A JP H01142472A
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- lead
- contact
- conductor
- pusher
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 239000004020 conductor Substances 0.000 claims description 25
- 238000005452 bending Methods 0.000 abstract description 5
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000000428 dust Substances 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は半導体素子（以下、ＩＣという）の電気的特性
を試験する際に使用される半導体素子検査用コンダクタ
に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a conductor for testing semiconductor devices used when testing the electrical characteristics of semiconductor devices (hereinafter referred to as ICs).
［従来の技術］
従来、ＩＣの電気的特性を試験する場合には、コンダク
タの接触子をＩＣのリードに１本づつ接触させ、この接
触子を介してＩＣのリードとテスタとを電気的に接続し
てＩＣの電気的特性を試験している。[Prior Art] Conventionally, when testing the electrical characteristics of an IC, the contacts of a conductor are brought into contact with the leads of the IC one by one, and the leads of the IC and the tester are electrically connected through the contacts. Connected to test the electrical characteristics of the IC.
［発明が解決しようとする問題点］
しかしながら、上述した従来のコンダクタにおいては、
ＩＣのリードを１本づつ接触子により接触させるため、
接触子の曲がり又は破損が発生しやすい、そして、この
ような接触子の曲がり又は破損が発生すると、接触不良
が生じ、電気的特性試験が不能になるという問題点があ
る。[Problems to be solved by the invention] However, in the conventional conductor described above,
In order to contact each IC lead one by one with a contactor,
There is a problem that bending or breakage of the contact easily occurs, and when such bending or breakage of the contact occurs, a contact failure occurs and an electrical characteristic test becomes impossible.
本発明はかかる問題点に鑑みてなされたものであって、
接触不良が生じて特性試験が不能になることが防止され
、確実にＩＣの電気的特性を試験することができる半導
体素子検査用コンダクタを提供することを目的とする。The present invention has been made in view of such problems, and includes:
It is an object of the present invention to provide a conductor for testing a semiconductor device, which prevents failure of a characteristic test due to poor contact and allows reliable testing of the electrical characteristics of an IC.
［問題点を解決するための手段］
本発明に係る半導体素子検査用コンダクタは、コンダク
タ本体と、このコンダクタ本体に形成され半導体素子の
リードに整合する形状の導電性膜のパターンと、このパ
ターンが形成された領域に設けられ前記パターンの延長
方向に実質的に直交する稜線を有する凹凸形状と、前記
半導体素子のリードをパターンに押し付けるプッシャと
、を有することを特徴とする。[Means for Solving the Problems] A conductor for testing semiconductor devices according to the present invention includes a conductor body, a conductive film pattern formed on the conductor body and having a shape that matches the leads of the semiconductor device, and this pattern formed on the conductor body. It is characterized by having an uneven shape provided in the formed region and having a ridgeline substantially perpendicular to the extending direction of the pattern, and a pusher for pressing the lead of the semiconductor element against the pattern.
［作用］
本発明においては、コンダクタ本体に形成された導電性
膜のパターンに半導体素子のリードを直接接触させる。[Operation] In the present invention, the leads of the semiconductor element are brought into direct contact with the conductive film pattern formed on the conductor body.
そして、コンダクタ本体にはこのパターン形成領域に凹
凸形状を形成しであるがら、プッシャにより半導体素子
のリードをパターンに押し付けることにより、前記リー
ドに前記凹凸形状がくい込んでリードとパターンとが確
実に接触する。Then, while an uneven shape is formed in the pattern forming area of the conductor body, when the lead of the semiconductor element is pressed against the pattern by a pusher, the uneven shape sinks into the lead and the lead and pattern are securely contacted. do.
従って、本発明によれば、接触子の曲がり又は破損等に
よる接触不良が回避され、パターンにより半導体素子の
リードを確実に電気的に導出することができる。Therefore, according to the present invention, poor contact due to bending or breakage of the contactor can be avoided, and the leads of the semiconductor element can be reliably electrically guided through the pattern.
［実施例］
次に、本発明の実施例について添付の図面を参照して説
明する。[Example] Next, an example of the present invention will be described with reference to the accompanying drawings.
第１図は本発明の実施例に係る半導体素子検査用コンダ
クタを示す縦断面図、第２図は同じくその平面図である
。絶縁性材料からなるコンダクタ本体１の上面には、Ｉ
Ｃ２の複数本のり−ド３に整合する形状のパターン４が
導電性膜をパターニングすることにより形成されている
。そして、このパターン４の形成領域には、凹凸形状５
が形成されている。この凹凸形状５はその稜線がパター
ン４の延長方向に直交する。FIG. 1 is a longitudinal sectional view showing a conductor for testing semiconductor devices according to an embodiment of the present invention, and FIG. 2 is a plan view thereof. The upper surface of the conductor body 1 made of an insulating material has I
A pattern 4 having a shape matching the plurality of boards 3 of C2 is formed by patterning a conductive film. Then, in the formation area of this pattern 4, an uneven shape 5 is formed.
is formed. The ridgeline of this uneven shape 5 is orthogonal to the extending direction of the pattern 4.
コンダクタ本体１の下面には配線８が形成されており、
この配線８とコンダクタ本体１の上面のパターン５とは
コンダクタ本体１の厚さ方向に挿通するスルーパターン
９により電気的に接続されている。Wiring 8 is formed on the lower surface of the conductor body 1.
This wiring 8 and the pattern 5 on the upper surface of the conductor body 1 are electrically connected by a through pattern 9 inserted through the conductor body 1 in the thickness direction.
プッシャ６はその下面がコンダクタ本体のパターン４及
び凹凸形状５の形成領域に整合する領域にて下方に突出
し、押付部７を形成している。The pusher 6 has a lower surface that protrudes downward in a region that matches the formation region of the pattern 4 and the uneven shape 5 of the conductor body, and forms a pressing portion 7.
このように構成された半導体素子検査用コンダクタにお
いては、ＩＣ２をコンダクタ本体１のパターン形成領域
の中央に載置し、ＩＣ２のリード３をパターン４に整合
させて接触させる。そして、プッシャ６をコンダクタ本
体１に向けて押し付けると、プッシャ６の押付部７によ
りリード３がコンダクタ本体１のパターン４に押し付け
られ、凹凸形状５がリード３にくい込む。これにより、
リード３がパターン５に電気的に接続される。そして、
コンダクタ本体１の下面の配線８をテスタ（図示せず）
に接続することにより、スルーパターン９及びパターン
５を介して、ＩＣ２のり−ド３がテスタに電気的に接続
される。In the conductor for testing semiconductor devices configured in this manner, the IC 2 is placed in the center of the pattern forming area of the conductor body 1, and the leads 3 of the IC 2 are aligned with and brought into contact with the pattern 4. Then, when the pusher 6 is pressed toward the conductor body 1, the lead 3 is pressed against the pattern 4 of the conductor body 1 by the pressing portion 7 of the pusher 6, and the uneven shape 5 sinks into the lead 3. This results in
Lead 3 is electrically connected to pattern 5. and,
Test the wiring 8 on the bottom of the conductor body 1 using a tester (not shown).
By connecting to the through pattern 9 and the pattern 5, the IC2 board 3 is electrically connected to the tester.
本実施例においては、接触子をＩＣ２のリード３に１本
づつ接触させるのではなく、パターン４によりまとめて
押圧接触させるので、接触子の曲がり又は破損等が発生
せず、確実にリード３を外部に電気的に導出することが
できる。また、凹凸形状５がＩＣ２のり−ド３にくい込
むので、パターン４の表面が油分又はゴミ等により汚染
されていても、接触不良が生じることなく確実にリード
３とパターン４とを接続することができる。In this embodiment, the contacts are not brought into contact with the leads 3 of the IC 2 one by one, but are brought into pressure contact all at once using the pattern 4, so that bending or damage of the contacts does not occur, and the leads 3 are reliably contacted. It can be electrically led out. In addition, since the uneven shape 5 sinks into the IC2 adhesive 3, even if the surface of the pattern 4 is contaminated with oil or dust, the lead 3 and pattern 4 can be reliably connected without causing contact failure. can.
［発明の効果］
以上説明したように本発明によれば、リードをパターン
に接触させることにより、リードとパターンとを電気的
に接続して導出するから、接触子の曲がり又は破損の虞
れが全くなくなり、確実にリードとテスタとを接続する
ことができる。[Effects of the Invention] As explained above, according to the present invention, the lead and the pattern are electrically connected and led out by bringing the lead into contact with the pattern, so there is no risk of the contactor being bent or damaged. The lead and tester can be reliably connected.
また、凹凸形状がＩＣリードへくい込むので、パターン
表面の油分又はゴミ等の汚染による接触不良も回避され
るという効果を奏する。Furthermore, since the uneven shape digs into the IC lead, poor contact due to contamination such as oil or dust on the pattern surface can be avoided.
第１図は本発明の実施例に係る半導体素子検査用コンダ
クタを示す縦断面図、第２図はその平面図である。FIG. 1 is a longitudinal sectional view showing a conductor for testing semiconductor devices according to an embodiment of the present invention, and FIG. 2 is a plan view thereof.
Claims (1)
導体素子のリードに整合する形状の導電性膜のパターン
と、このパターンが形成された領域に設けられ前記パタ
ーンの延長方向に実質的に直交する稜線を有する凹凸形
状と、前記半導体素子のリードをパターンに押し付ける
プッシャと、を有することを特徴とする半導体素子検査
用コンダクタ。It has a conductor body, a conductive film pattern formed on the conductor body and having a shape that matches the leads of the semiconductor element, and a ridge line provided in the area where the pattern is formed and substantially orthogonal to the extending direction of the pattern. A conductor for testing a semiconductor device, characterized in that it has an uneven shape and a pusher that presses the lead of the semiconductor device against the pattern.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62301829A JP2583252B2 (en) | 1987-11-30 | 1987-11-30 | Contactor for semiconductor device inspection |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62301829A JP2583252B2 (en) | 1987-11-30 | 1987-11-30 | Contactor for semiconductor device inspection |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01142472A true JPH01142472A (en) | 1989-06-05 |
| JP2583252B2 JP2583252B2 (en) | 1997-02-19 |
Family
ID=17901660
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62301829A Expired - Fee Related JP2583252B2 (en) | 1987-11-30 | 1987-11-30 | Contactor for semiconductor device inspection |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2583252B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04120233U (en) * | 1991-04-11 | 1992-10-27 | 富士通株式会社 | Semiconductor characteristic evaluation equipment |
-
1987
- 1987-11-30 JP JP62301829A patent/JP2583252B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04120233U (en) * | 1991-04-11 | 1992-10-27 | 富士通株式会社 | Semiconductor characteristic evaluation equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2583252B2 (en) | 1997-02-19 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |