JPS63236978A - Socket for measurement - Google Patents

Socket for measurement

Info

Publication number
JPS63236978A
JPS63236978A JP7287887A JP7287887A JPS63236978A JP S63236978 A JPS63236978 A JP S63236978A JP 7287887 A JP7287887 A JP 7287887A JP 7287887 A JP7287887 A JP 7287887A JP S63236978 A JPS63236978 A JP S63236978A
Authority
JP
Japan
Prior art keywords
leads
semiconductor device
wiring pattern
opening part
insulating substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7287887A
Inventor
Hiromi Takano
Original Assignee
Nec Kyushu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Kyushu Ltd filed Critical Nec Kyushu Ltd
Priority to JP7287887A priority Critical patent/JPS63236978A/en
Publication of JPS63236978A publication Critical patent/JPS63236978A/en
Application status is Pending legal-status Critical

Links

Abstract

PURPOSE: To prevent the leads of a semiconductor device from bending or flawing by bringing the wiring pattern of an insulating substrate into surface contact with the leads of the semiconductor device and forming a clearance hole for the semiconductor device as a substitute for positioning separators for the leads.
CONSTITUTION: A socket has an opening part 2 as the clearance hole for the semiconductor device 5 formed on the insulating substrate 1, an elastic insulating resin 3 formed on the insulating substrate 1 while covering the periphery of the opening part 2, and the conductive metallic wiring pattern 4 formed toward the opening part 2 while straddling said resin 3 and the top surface of the insulating substrate 1. Then when the socket is used, the semiconductor device 5 is placed at the opening part 2 and pressure is applied to the leads 7 and wiring pattern 4 by a pressing-down means such as a pressure plate 6. Consequently, the elastic insulating resin 3 is compressed to bring the wiring pattern and the leads 7 of the semiconductor device 5 into contact each other, so that the leads neither flaw nor bend.
COPYRIGHT: (C)1988,JPO&Japio
JP7287887A 1987-03-25 1987-03-25 Socket for measurement Pending JPS63236978A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7287887A JPS63236978A (en) 1987-03-25 1987-03-25 Socket for measurement

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7287887A JPS63236978A (en) 1987-03-25 1987-03-25 Socket for measurement

Publications (1)

Publication Number Publication Date
JPS63236978A true JPS63236978A (en) 1988-10-03

Family

ID=13502029

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7287887A Pending JPS63236978A (en) 1987-03-25 1987-03-25 Socket for measurement

Country Status (1)

Country Link
JP (1) JPS63236978A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05259304A (en) * 1992-03-12 1993-10-08 Yamaichi Electron Co Ltd Ic carrier
US6320398B1 (en) 1996-08-09 2001-11-20 Advantest Corporation Semiconductor device testing apparatus

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05259304A (en) * 1992-03-12 1993-10-08 Yamaichi Electron Co Ltd Ic carrier
US6320398B1 (en) 1996-08-09 2001-11-20 Advantest Corporation Semiconductor device testing apparatus

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