JPH01140835U - - Google Patents

Info

Publication number
JPH01140835U
JPH01140835U JP3809588U JP3809588U JPH01140835U JP H01140835 U JPH01140835 U JP H01140835U JP 3809588 U JP3809588 U JP 3809588U JP 3809588 U JP3809588 U JP 3809588U JP H01140835 U JPH01140835 U JP H01140835U
Authority
JP
Japan
Prior art keywords
pair
elements
bonding pad
circuit device
wired
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3809588U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP3809588U priority Critical patent/JPH01140835U/ja
Publication of JPH01140835U publication Critical patent/JPH01140835U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は実施例の回路装置を示す上面透視図、
第2図は一般的な回路図、第3図は従来の技術の
回路装置を示す上面透視図である。 1,2…素子、3…プツシユプル回路、4…制
御回路、5,51,52…ボンデイングパツド、
6…スルーホール、7…クロスアンダ配線、81
,82,91…共通線。
FIG. 1 is a top perspective view showing the circuit device of the embodiment;
FIG. 2 is a general circuit diagram, and FIG. 3 is a top perspective view showing a conventional circuit device. 1, 2... Element, 3... Push-pull circuit, 4... Control circuit, 5, 51, 52... Bonding pad,
6...Through hole, 7...Cross under wiring, 81
, 82, 91... common line.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 一対の素子の両ドレンをボンデイングパツドに
配線し、前記一対の素子を複数対配置した各素子
のソースを各チヤンネル毎に一対の共通線に配線
してなるものにおいて、前記ボンデイングパツド
を前記一対の素子の間に配置し、前記一対の共通
線をそれぞれ前記一対の素子の外側に配置するこ
とを特徴とするC―MOS FET集積回路装置
Both drains of a pair of elements are wired to a bonding pad, and the source of each element in which a plurality of pairs of the pair of elements are arranged is wired to a pair of common lines for each channel, wherein the bonding pad is connected to the bonding pad. A C-MOS FET integrated circuit device, wherein the C-MOS FET integrated circuit device is disposed between a pair of elements, and the pair of common lines are respectively disposed outside the pair of elements.
JP3809588U 1988-03-23 1988-03-23 Pending JPH01140835U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3809588U JPH01140835U (en) 1988-03-23 1988-03-23

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3809588U JPH01140835U (en) 1988-03-23 1988-03-23

Publications (1)

Publication Number Publication Date
JPH01140835U true JPH01140835U (en) 1989-09-27

Family

ID=31264667

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3809588U Pending JPH01140835U (en) 1988-03-23 1988-03-23

Country Status (1)

Country Link
JP (1) JPH01140835U (en)

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