JPH022848U - - Google Patents
Info
- Publication number
- JPH022848U JPH022848U JP7934688U JP7934688U JPH022848U JP H022848 U JPH022848 U JP H022848U JP 7934688 U JP7934688 U JP 7934688U JP 7934688 U JP7934688 U JP 7934688U JP H022848 U JPH022848 U JP H022848U
- Authority
- JP
- Japan
- Prior art keywords
- output
- planar
- lines
- drivers
- areas
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 3
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Description
第１図は本考案の実施例に係る半導体チツプに
おける入出力インタフエース領域の平面図である
。第２図は従来例に係る第１図に対応する平面図
である。
２……入出力インタフエース領域、４……電源
ライン、６……接地ライン、８，１０，１２，１
４……第１の出力ドライバ、８ｄ，１０ｄ，１２
ｄ，１４ｄ……第１の出力ドライバの平面領域、
１６，１８，２０，２２……出力パツド、２４，
２６，２８，３０……接続配線、３６，３８，４
０，４２，４４……第２の出力ドライバ。
FIG. 1 is a plan view of an input/output interface area in a semiconductor chip according to an embodiment of the present invention. FIG. 2 is a plan view corresponding to FIG. 1 according to a conventional example. 2... Input/output interface area, 4... Power line, 6... Ground line, 8, 10, 12, 1
4...First output driver, 8d, 10d, 12
d, 14d...Planar area of the first output driver,
16, 18, 20, 22... Output pad, 24,
26, 28, 30... Connection wiring, 36, 38, 4
0, 42, 44...second output driver.
Claims (1)
とで囲まれた入出力インタフエース領域面内にお
いて、複数の第１の出力ドライバ形成用としてこ
れと同数対の平面領域が、その各対ごとに所定間
隔を隔てて前記両ラインの延設方向に沿つてかつ
当該両ラインのそれぞれに相対向するようにレイ
アウトされており、また、相対向する前記各対ご
との平面領域間のそれぞれには、対応する前記第
１の出力ドライバそれぞれの出力部に接続配線さ
れた出力パツドがレイアウトされてなるものであ
つて、 前記各ラインの延設方向において互いに対向す
る前記第１の出力ドライバそれぞれの平面領域の
間に、第２の出力ドライバ形成用としての平面領
域がレイアウトされており、任意の第１の出力ド
ライバの出力パツドが前記第２の出力ドライバの
１つまたは複数に接続配線されたレイアウトを有
することを特徴とする、半導体チツプにおける入
出力インタフエース領域の平面レイアウト構造。[Claims for Utility Model Registration] Within the plane of the input/output interface area surrounded by the power supply line and the ground line in the semiconductor chip, the same number of pairs of plane areas are provided for forming a plurality of first output drivers. Each pair is laid out at a predetermined interval along the extending direction of the two lines and facing each of the two lines, and between the planar areas of each pair facing each other. Each of the lines has output pads connected and wired to the output parts of the corresponding first output drivers, and the first output drivers face each other in the extending direction of each line. A planar area for forming a second output driver is laid out between the respective planar areas, and an output pad of an arbitrary first output driver is connected to one or more of the second output drivers by wiring. 1. A planar layout structure of an input/output interface area in a semiconductor chip, characterized by having a layout according to the invention.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7934688U JPH022848U (en) | 1988-06-15 | 1988-06-15 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7934688U JPH022848U (en) | 1988-06-15 | 1988-06-15 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH022848U true JPH022848U (en) | 1990-01-10 |
Family
ID=31304231
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7934688U Pending JPH022848U (en) | 1988-06-15 | 1988-06-15 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH022848U (en) |
-
1988
- 1988-06-15 JP JP7934688U patent/JPH022848U/ja active Pending