JPS6240836U - - Google Patents
Info
- Publication number
- JPS6240836U JPS6240836U JP13189485U JP13189485U JPS6240836U JP S6240836 U JPS6240836 U JP S6240836U JP 13189485 U JP13189485 U JP 13189485U JP 13189485 U JP13189485 U JP 13189485U JP S6240836 U JPS6240836 U JP S6240836U
- Authority
- JP
- Japan
- Prior art keywords
- chip
- gates
- internal wiring
- wire bonding
- bonding pads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
第１図は本考案の一実施例のワイヤボンデイン
グチツプの配線構造の模式図、第２図は一実施例
の配線模式図、第３図は従来のワイヤボンデイン
グチツプの模式図を示す。
図において、１はチツプ、１―１〜１―ｎは入
出力用ボンデイングパツト、２―１〜２―ｎはゲ
ート、３は内部配線領域、４―１〜４―ｎはボン
デイングパツトを示している。
FIG. 1 is a schematic diagram of the wiring structure of a wire bonding chip according to one embodiment of the present invention, FIG. 2 is a schematic diagram of the wiring structure of one embodiment, and FIG. 3 is a schematic diagram of a conventional wire bonding chip. In the figure, 1 is a chip, 1-1 to 1-n are input/output bonding pads, 2-1 to 2-n are gates, 3 is an internal wiring area, and 4-1 to 4-n are bonding pads. There is.
Claims (1)
２―ｎと、前記各ゲートを内部接続する接続線と
より成る集積回路部品のワイヤボンデイングチツ
プにおいて、前記各ゲートのそれぞれと接続する
内部配線用ボンデイングパツト４４―１〜４４―
ｎをチツプ面にエリアアレイ状に配設し、前記配
設された所定の内部配線用ボンデイングパツト間
をデイスクリート線により接続するようにしたこ
とを特徴とするワイヤボンデイングチツプの配線
構造。 A plurality of gates 2-1~ formed in the chip 1
In a wire bonding chip for an integrated circuit component consisting of a wire bonding chip 2-n and a connection line that internally connects each of the gates, bonding pads 44-1 to 44- for internal wiring connect to each of the gates, respectively.
1. A wiring structure for a wire bonding chip, characterized in that bonding pads for internal wiring are arranged in an area array on a chip surface, and discrete wires are used to connect predetermined bonding pads for internal wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13189485U JPS6240836U (en) | 1985-08-28 | 1985-08-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13189485U JPS6240836U (en) | 1985-08-28 | 1985-08-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6240836U true JPS6240836U (en) | 1987-03-11 |
Family
ID=31030767
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13189485U Pending JPS6240836U (en) | 1985-08-28 | 1985-08-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6240836U (en) |
-
1985
- 1985-08-28 JP JP13189485U patent/JPS6240836U/ja active Pending
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