JPH01137539U - - Google Patents
Info
- Publication number
- JPH01137539U JPH01137539U JP3399288U JP3399288U JPH01137539U JP H01137539 U JPH01137539 U JP H01137539U JP 3399288 U JP3399288 U JP 3399288U JP 3399288 U JP3399288 U JP 3399288U JP H01137539 U JPH01137539 U JP H01137539U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor component
- top surface
- heat sink
- printed wiring
- wiring board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 6
- 239000011347 resin Substances 0.000 claims description 2
- 229920005989 resin Polymers 0.000 claims description 2
- 238000009413 insulation Methods 0.000 claims 1
- 239000000463 material Substances 0.000 claims 1
Description
第１図は本考案一実施例の要部斜視図、第２図
は同上の要部断面図、第３図はさらに他の実施例
の要部斜視図、第４図は同上の要部断面図、第５
図は従来例の斜視図、第６図は他の従来例の斜視
図、第７図は同上の要部断面図、第８図はさらに
他の従来例の要部斜視図、第９図はさらに他の従
来例の要部断面図である。
１は絶縁板、３は配線パターン、４はプリント
配線基板、５は半導体部品、６は放熱板、７は凹
凸、８はモールド樹脂層である。
Fig. 1 is a perspective view of a main part of an embodiment of the present invention, Fig. 2 is a cross-sectional view of a main part of the same as above, Fig. 3 is a perspective view of a main part of another embodiment, and Fig. 4 is a cross-section of a main part of the same as above. Figure, 5th
The figure is a perspective view of a conventional example, FIG. 6 is a perspective view of another conventional example, FIG. 7 is a sectional view of the same essential parts as above, FIG. FIG. 7 is a sectional view of a main part of still another conventional example. 1 is an insulating plate, 3 is a wiring pattern, 4 is a printed wiring board, 5 is a semiconductor component, 6 is a heat sink, 7 is an uneven surface, and 8 is a molded resin layer.
Claims (1)
板上に複数の半導体部品を実装し、各半導体部品
の上面に一面が密着され他面の面積が半導体部品
の上面の面積よりも広い良熱伝導性絶縁物よりな
る放熱板を半導体部品の上面に密着配置し、半導
体部品および放熱板が実装されたプリント配線基
板全体を樹脂モールドしたことを特徴とするハイ
ブリツド集積回路。 Multiple semiconductor components are mounted on a printed wiring board with a wiring pattern on an insulating board, and one side is tightly attached to the top surface of each semiconductor component, and the area of the other surface is larger than the top surface of the semiconductor component.Insulation with good thermal conductivity. 1. A hybrid integrated circuit characterized in that a heat sink made of a material is closely placed on the top surface of a semiconductor component, and the entire printed wiring board on which the semiconductor component and the heat sink are mounted is molded with resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3399288U JPH01137539U (en) | 1988-03-15 | 1988-03-15 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3399288U JPH01137539U (en) | 1988-03-15 | 1988-03-15 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01137539U true JPH01137539U (en) | 1989-09-20 |
Family
ID=31260711
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3399288U Pending JPH01137539U (en) | 1988-03-15 | 1988-03-15 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01137539U (en) |
-
1988
- 1988-03-15 JP JP3399288U patent/JPH01137539U/ja active Pending