JPH01136205A - Input circuit for programmable controller - Google Patents

Abstract

PURPOSE:To easily catch a specified pulse by storing the specified pulse to a second memory with the interruption processing of a central operation processor when the specified pulse with non-synchronizing to a timing to write a signal from plural external input contacts to the second memory. CONSTITUTION:The title circuit is composed of an external power source 1 to supply a voltage to a photocoupler 6, an external relay contact 2 to input information by turning on and off the voltage which is supplied from this power source, power source connecting terminals 3 and 4, a current limiting resistance 5, a load resistance 7, an inverter 8, filters 9 and 10, an interface 11, a CPU 12 and a memory 13, etc. By charging the power source, the CPU 12 allows the input of an interrupting signal. Next, the CPU 12 reads the storing contents of the memory 13 and executes prescribed sequence operation. A memory 13-1 is referred for the CPU 12 and when the memory is turned on, decision is made as the input of a high speed pulse. Then, input and output processings to an external equipment are totally executed. Next, the memory 13-1 is cleared and one time scanning operation is finished.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an input circuit for a programmable controller.

[Prior Art] In general, a programmable controller inputs relay on/off information from an external device and performs sequence calculations.
It is known as a controller that turns on/off the above relay or other relays according to calculation results.

For this purpose, the programmable controller uses input relay on/off information (input information) and relay on/off information.
Memory for storing information to be turned off (output information), sequence operations, writing input information to memory,
It has a central processing unit (CPU) that reads output information from memory and outputs it to external equipment.

In addition, the CPU executes a predetermined program,
The above process is being performed. Since the processing speed of the CPU is relatively fast, it is possible to store changed input information in memory in response to changes in input information from external devices. If the input information changes on-off-on like a pulse while performing such a sequence operation, the CPU is not executing the program to write the input information to the memory. This changed input information cannot be stored in the memory on the CPU side. For this reason, there has been a demand for input information in the form of high-speed pulses generated asynchronously to a programmable controller.

In response to this demand, conventional programmable controllers and information input methods for programmable controllers have the following drawbacks.

(1) A batch processing type programmable controller cannot capture inputs that are not synchronized with the timing of batch processing of human outputs, and therefore cannot capture high-speed pulses.

(2) On the other hand, high-speed pulses are captured in input/output direct processing type programmable controllers, that is, programmable controllers that perform external and human output in synchronization with the execution of input or output commands during sequence operations. In order to do this, the sequence must be programmed to always input high-speed pulses, which is not practical.

(3) A known method is to use an interrupt program to interrupt the programmable controller at the moment a high-speed pulse is captured, and to execute a sequence corresponding to the pulse input. However, with this method, it is difficult to synchronize with the normal sequence, and the burden on the user's program is large.

(4) Therefore, a method is also known in which special hardware for capturing high-speed pulses is prepared, and the problems caused by program processing are solved as described above, and the input is performed. Two representative examples are shown below.

In the first example, a monostable multivibrator is added to the input circuit, and a high-speed pulse is used as a trigger to obtain a pulse output with a predetermined pulse width, thereby extending the pulse width of the high-speed pulse and capturing it.

In the second example, a flip-flop is added to the input circuit,
This flip-flop is set with a fast pulse to capture and store the fast pulse.

[Problems to be Solved by the Invention] However, in the first example described above, there is a drawback that this method cannot be used if the scan time of the programmable controller becomes longer than the set time of the monostable multivibrator.

Also, in the second example, in order to capture the next high-speed pulse,
A circuit is required to reset the flip-flop once. Furthermore, a sequence for determining the timing for resetting this flip-flop by the reset circuit must be programmed into the programmable controller, which increases the burden on the user.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to solve the above-mentioned drawbacks of the prior art, and to solve the problem of generating data asynchronously with the scan of the programmable controller without increasing the cost of hardware and without imposing a burden on the user on the sequence program. An object of the present invention is to provide a high-speed pulse input circuit that can capture a single high-speed pulse generated by a pulse input and that does not impose any burden on a sequence program even to a user who does not require pulse input.

[Means for Solving the Problems] In order to achieve such an object, the present invention provides a first storage means for storing a first signal, a second storage means for storing a second signal, and a predetermined storage means for storing a first signal. a central processing unit that writes a first signal from one or more external input contacts into a first storage means in synchronization with timing, and writes a second signal indicating an input into a second storage means in response to input of an interrupt signal; A specific external input contact among the external input contacts includes a signal transmission means for inputting a specific signal generated asynchronously at a predetermined timing to an interrupt input terminal of the central processing unit as an interrupt signal. shall be.

[Function] In the present invention, when a specific pulse that is asynchronous to the timing at which signals from multiple external input contacts are written to the second memory is generated, this specific pulse serves as a trigger, and the asynchronous processing is performed by the interrupt processing of the central processing unit. Since the occurrence of the specific pulse is stored in the second storage means, the asynchronous specific pulse can be captured with a simple configuration.

[Example] An example of the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows an example of a circuit configuration according to an embodiment of the present invention.

In FIG. 1, reference numeral 1 denotes an external power supply that supplies voltage to the photocoupler 6. 2 is an external relay contact that inputs information by turning on and off a voltage supplied from an external power source. 6 is a photocoupler that transmits on/off information inputted through an external relay contact to the programmable controller side.

3 and 4 are power supply connection terminals for connection to an external power supply, and 5 is a current limiting resistor for setting the power supply voltage to the operating voltage of the photocoupler 6.

Reference numeral 7 denotes a load resistor that sets the voltage level of the ON information received on the programmable controller side. 8 is an inverter that inverts the output signal level of the photocoupler 6 so that the CPU 12 can judge the on/off information received by the photocoupler 6.

9 and 10 are filters for removing noise in the output signal of the inverter 8; filter 9 is used for high-speed pulses, and filter 10 is used for normal signals. Further, the time constant of the filter 9 is set to be smaller than the time constant of the filter 10. Therefore, the high-speed pulse waveform ON information received by the photocoupler 6 is absorbed by the filter 10 and passes only through the filter 9.

11 is an interface that receives the normal waveform on/off information that has passed through the filter 10, and under the control of the CPU 12, the on/off information received by the interface 11 is
The off information (first signal) is stored in the memory 13 via the data bus DB. The on/off information of the pulse waveform that has passed through the filter 9 is sent to the interrupt signal input terminal of the CPU 12.

12 is a CPU that controls the programmable controller
It is. 13 is a memory (first storage means) that stores on/off information of a plurality of external contacts including external contact 2;

The memory 13 includes a pulse detection memory 13-1 that stores the presence or absence of an interrupt signal as on/off information (second signal).
(second storage means) is provided.

In such a configuration, when a scan-asynchronous, single-shot, high-speed pulse-like on/off signal from the external contact 2 is input to the interrupt input terminal of the CPU 12, the CPU 1 during scanning
2, the CPt 112 stores the fact that a high-speed pulse signal has been input in the pulse detection memory 13-1, and stores the corresponding high-speed pulse input contact memory in the memory 13 in synchronization with the normal input/output car batch processing. Turns on for one scan only.

Here, the CPU 12 always scans with interrupt input enabled, so that the input of the high-speed pulse signal is not missed. Further, when the external contact 2 is turned on for several scans, the high-speed pulse input contact memory remains turned on for the corresponding scan time.

Figures 2 (A) and (B) show the CPU 12 shown in Figure 1.
This figure shows the execution control procedure in 2.

In FIG. 2(A), when the programmable controller is powered on, the CpH 12 allows input of an interrupt signal (step Sl). Next, the CPU 12 reads out the contents of the memory 13 and performs a predetermined sequence calculation (step S2).

Next, the CPU 12 refers to the pulse detection memory 13-1, and when the pulse detection memory 13-1 is on, it determines that there is a high-speed pulse input, and corresponds to the external contact 2 in the memory 13. At the same time, input processing of information from the external device side and processing of outputting information to the external device are performed at once (steps 53 to S4).
.

Next, the pulse detection memory 13-1 is cleared to complete one scanning process. If an interrupt occurs due to a high-speed pulse while executing such a procedure, the CPII 12 executes the control procedure shown in FIG. 2(B) and stores the pulse detection memory 1.
3-1 is turned on to return to the control procedure shown in FIG. 2 (8).

FIG. 3 shows the operation timing of the embodiment of the present invention.

In FIG. 3, if the external contact 2 happens to turn on/off in a high-speed pulse while the programmable controller is executing sequence a of scan a, the high-speed pulse signal is transmitted to the input terminal 4 - current limiting resistor 5 - photocoupler 6 - It passes through the inverter 8 (see FIG. 1) and is transmitted to the high-speed pulse filter a and the normal filter lO.

The pulses transmitted to each filter are the normal filter IO
In this case, the signal disappears and is not normally transmitted to the input signal line.

On the other hand, in the temporal high-speed pulse filter 9, the pulse is transmitted to the high-speed pulse input signal line P, although there is a delay due to the filter time.

The high-speed pulse transmitted to the high-speed pulse input signal line P is
12, and the CPU 12 stores the fact that the pulse has been input into the pulse detection memory 13-1 in the memory 13 through the data bus DB.

When the execution of scan a enters the turnout car batch process (process 110a in FIG. 3), the CPU 12 reads the pulse detection memory, and if the memory content is on, reads the corresponding pulse input contact memory in the memory 13. is turned on to clear the contents of the pulse detection memory 13-1.

Next, the scan is scan b input/output car batch processing (processing 1
10b), the CPU 112 confirms that the pulse detection memory is not turned on and that the high-speed pulse input signal line is not turned on, and stores that the pulse detection memory 13-1 is off.

Scans c, d, and e show the operation when the external contact 2 is on for a long time, and it can be seen that the pulse detection memory 13-1 operates in the same way as the normal input contact memory 13 at this time. Karu.

Also, it passes through the normal filter 10 → normal input signal line, and the I
The signal transmitted to lo 11 has a long filter time to prevent chattering that occurs when external contact 2 turns on and off.

Moreover, the timing at which the CPU 12 scans the signal and reflects it in the memory 13 is performed in synchronization with the crowd car batch processing. Incidentally, a user who does not require high-speed pulse input, that is, who does not want the user to react to chattering of the external contact 2, may use only this normal input.

In this embodiment, the filter 9 and the filter 10 are CR filters composed of capacitors and resistors, but it is clear that the same operation can be performed using software filters or the like.

[Effects of the Invention] As explained above, according to the present invention, a signal sent from a specific external input contact among the external input contacts is transmitted to the CPU.
is connected to the interrupt input of CPt1, and the high-speed pulse generation of a specific external input contact is detected by the interrupt processing of CPt1, so there is no need to significantly change conventional hardware or increase costs. It is possible to capture single high-speed pulses that occur asynchronously with the scan of the programmable controller without placing any burden on the program, and does not impose any burden on users who do not require pulse input. This effect can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a configuration example of an embodiment of the present invention, FIG. 2 is a flowchart showing an example of an execution control procedure of the CPU 12 shown in FIG. 1, and FIG. 3 is a timing chart showing the operation timing of the embodiment of the present invention. be. 2... External contact, 6... Photocoupler, 9.10... Filter, 12... CPU. 13...Memory. Orishiri Monthly Tribute Begging Column 0 Flowchart Figure 2

Claims (1)

[Claims] 1) A first storage means for storing a first signal, a second storage means for storing a second signal, and a first signal from one or more external input contacts in synchronization with a predetermined timing. a central processing unit that writes a second signal indicating the input into the first storage means and writes a second signal indicating the input into the second storage means in response to an input of an interrupt signal; An input circuit for a programmable controller, characterized in that the input circuit comprises a signal transmission means whose contacts input a specific signal generated asynchronously at the predetermined timing to an interrupt input terminal of the central processing unit as the interrupt signal. 2) In the input circuit for a programmable controller according to claim 1, the signal transmission means includes a signal line for transmitting the specific signal as the first signal to the first storage means, and the signal line. a first filter for removing noise; a signal line for transmitting the specific signal as the interrupt signal to the interrupt input terminal; and a signal line for transmitting the specific signal as the interrupt signal to the interrupt input terminal; and a second filter for removing small noises.