JPH01134947A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To eliminate a failure due to the leak between element isolation regions by a method wherein an oxide film is formed on the side surfaces only of a groove to expose a substrate under the bottom surface of the groove, a diffused layer is grown in the groove and an impurity is diffused by heat treatment. CONSTITUTION:An Si oxide film 6 is formed on the side surfaces and the bottom surface of a groove 5a and the film 6 only on the bottom surface is removed to expose a substrate 1. A P-type impurity-containing spin-on-glass film 10 is grown in a groove 5. After that, a heat treatment is performed to form a P-type impurity diffused region 11 under the groove 5. A poly Si layer 12 is formed in the groove, the surface of the layer 12 is flattened by a polishing machine, an oxide film 2a is formed on the surface of the groove part and a nitride film 3 is removed.

Description

[Detailed Description of the Invention] [Summary] Regarding a method for manufacturing a semiconductor device having a groove (trench) used for element isolation, when forming a diffusion region in a channel cut region under the groove, there is no impact to the groove. , a process in which an oxide film is formed only on the side surfaces of the trench and the substrate is exposed on the bottom surface of the trench, with the aim of obtaining a sufficient dose barrier in the diffusion region and manufacturing with less damage and contamination to the wafer itself. a step of growing a diffusion source layer in the groove; and a step of diffusing impurities in the diffusion source layer into the substrate under the groove by heat treatment to form a diffusion region.

[Industrial application field]

The present invention relates to a method for manufacturing a semiconductor device having grooves used for element isolation.

In semiconductor devices with a so-called trench inlay structure in which trenches are provided for element isolation, a diffusion region is formed in the substrate under the trench to serve as a channel cut region, while polycrystalline silicon, etc. is buried in the trench. flatten the surface.

Therefore, when forming the above-mentioned diffusion region, it is desirable to manufacture it with fewer steps and without receiving any impact from the groove.

[Conventional technology]

FIG. 3 is a diagram showing a conventional manufacturing method. In the same figure (A>), for example, silicon oxide (Sf) is placed on the n-type substrate 1.
An oxide film 2 such as oxide film 2, a nitride film 4 such as silicon nitride (SiN), and a shielding film 4 such as PSG are formed in this order (including the broken line portion), and predetermined portions are removed by etching.

Next, etching is performed using the shielding film 4 as a mask.
), a layer 5a is formed and the shielding film 4 is removed.

Next, as shown in FIG. 5C, a silicon oxide film 6a having a thickness of, for example, 500 mm is formed on the side and bottom surfaces of the 58 mm.
After that, by ion-implanting boron (B+),
A p-type expanded rll region 7 is formed in the substrate 1 below the groove 58.

Next, as shown in FIG. 6(D), a silicon oxide film 6 is formed to a thickness of, for example, about 2,000 mm, and then,
As shown in FIG.
form.

Next, what about the surface of polycrystalline silicon layer 8? It was flattened using an iFf polisher as shown in the same figure (F), and then the same figure (
As shown in G), an oxide film 2a is formed on the surface of the groove portion,
Nitride Pa3 is removed.

[Problem that the invention seeks to solve]

In the above conventional example, ion implantation is performed when forming the diffusion region 7 in the step shown in FIG.
The impact is applied to the periphery of a, resulting in defects, and this defect limits the dose range.Furthermore, the use of a relatively expensive ion implantation device increases costs. . In addition, this conventional example uses a polishing machine for planarization, which causes impact to the wafer itself, and also has the problem of contaminating the wafer because an etching solution is used during polishing. .

To provide a method for manufacturing a semiconductor device, in which when forming a diffusion region in a channel cut region under a groove, the dose of the diffusion region can be maintained sufficiently without being affected by the groove, and the wafer itself can be manufactured with less impact and contamination. The purpose is to

[Means for solving problems]

The above problem is solved by the process of forming an oxide film only on the side surfaces of the trench to expose the substrate at the bottom of the trench, the step of growing a diffusion source layer in the trench, and the heat treatment to remove impurities from the diffusion source layer under the trench. A method for manufacturing a semiconductor device is characterized in that it includes a step of forming a diffusion region by diffusing into a substrate, and a step of forming a diffusion region includes forming a diffusion region by heat treatment and simultaneously treating the surface of the diffusion 8I layer by heat treatment. Each of these problems is solved by a method for manufacturing a semiconductor device characterized by a planarization step.

[Effect]

In the present invention, a diffusion source layer is completely formed, and impurities in the diffusion source layer are diffused into the substrate under the groove by heat treatment to form a diffusion region. As a result, unlike the conventional example in which the diffusion region is formed by ion implantation, no impact is applied to the groove, and no defects are generated, so that a sufficient dose increase can be obtained and manufacturing can be performed at low cost.

On the other hand, since the surface of the diffusion source layer is flattened by heat treatment, there is no impact on the wafer itself, and there is no contamination of the wafer, compared to the conventional method of flattening using a polishing machine using an etching solution. There's nothing to do.

[Example] FIG. 1 is a diagram showing a first example of the manufacturing method of the present invention. Up to the steps shown in FIG. 3(A) and (B),
Since this process is similar to the process of the conventional example shown in (B), the explanation thereof will be omitted. In FIG. 1C, a silicon oxide film 6 is formed on the side and bottom surfaces of the groove 5a shown in FIG. As shown, only the silicon oxide crotch 6 on the bottom surface is removed and the substrate 1 is
expose.

Next, as shown in FIG. 5E, an SOG (spin-on-glass) film 10 (diffusion source film) containing p-type impurities is grown in the groove 5, and then heat treatment is performed to form the groove 5. A lower p-type impurity diffusion region 11 is formed. In this case, since ion implantation is not performed to form the diffusion region as in the conventional example, no impact is applied to the periphery of the groove 5, and no defects are caused. It is possible to form a highly concentrated Boullanelle cut region.

Next, as shown in the figure (F), a polycrystalline silicon layer 12 is formed in the middle, and then, as shown in the figure (G), the surface of the polycrystalline silicon layer 12 is is planarized using a polisher, and then, as shown in FIG. 2H, an oxide film 2a is formed on the surface of the groove portion, and the nitride film 3 is removed.

The first embodiment described above is the same as the conventional example in that the wafer itself is subjected to impact during planarization and the wafer is contaminated, but since heat treatment is used when forming the diffusion region, there is no impact on the grooves. Furthermore, since the heat treatment equipment is cheaper than the ion implantation equipment and the like, the cost is low.

FIG. 2 is a diagram showing a second embodiment of the manufacturing method of the present invention. After the steps shown in FIGS. 1(A) to (D) are completed, this product undergoes the steps shown in FIG. 2 (A>. FIG. 2(A)
As shown in FIG. 2, an SOG layer 20a (diffusion source film) containing p-type impurities is formed inside the groove 5. Next, a heat treatment is performed to form a p-type impurity diffusion region 21 approximately 50 m below, as shown in FIG. At the same time, through heat treatment, SO
GG20a is melted and its surface is almost flattened, and SOG
FI20 is formed.

Next, as shown in FIG. 5C, the surface of the SOG film 20 is planarized by, for example, isotropic dry etching, and then, as shown in FIG. is formed, and the nitride film 3 is removed.

In the second embodiment, as in the first embodiment, since the heat treatment is performed, there is no impact on the grooves, a sufficient dose can be obtained, and the cost is low. Since the surface of the wafer 20 can be approximately flattened, the wafer itself can be made flat by a method such as dry etching, as shown in FIG. Moreover, it does not contaminate the wafer.

[Effects of the Invention] As explained above, according to the present invention, since the diffusion region is formed by heat treatment, there is no impact on the groove compared to the conventional example using ion implantation, and the dose amount can be sufficiently controlled. Therefore, the element valve 111t can have a high withstand pressure.
It is possible to eliminate defects due to leakage between the lT4 regions, and since the heat treatment equipment 4 is cheaper than the ion implantation equipment, the cost is 1! lower than the conventional example using ion implantation. ! Furthermore, since the surface of the diffusion m-layer can be flattened by heat treatment, there is no impact on the wafer itself compared to the method using a polisher, and since no etching solution is used, there is no possibility of contaminating the wafer. Nor.

[Brief explanation of the drawing]

1 and 2 are diagrams showing a first and second embodiment of the liI manufacturing method of the present invention, respectively, and FIG. 3 is a diagram showing a conventional manufacturing method. In the figure, 1 is an n-type substrate, 2.28.6 is an oxide film, 3 is a nitride film, 5.5a is a groove, 10.20a, 20 is an SOG film containing p-type impurities (diffusion source WA), 800 Layer (diffusion source layer) 11.21 is a diffusion region, and 12 is a polycrystalline silicon layer. (A) (E) Figure 1 2 showing the second embodiment of the manufacturing method of the present invention ""=----"-7 Figure 3 showing the conventional manufacturing method

Claims (3)

[Claims] (1) In a method for manufacturing a semiconductor device with a trench isolation structure, in which a groove (5a) is formed in a substrate (1) and diffusion regions (11) and (21) are formed therebelow, the groove (5a) is forming an oxide film (6) only on the side surfaces to expose the substrate (1) at the bottom of the groove (5a); and growing diffusion source layers (10) and (20) in the groove (5). , Diffuse the impurities in the diffusion source layers (10) and (20) into the substrate (1) under the groove (5) by heat treatment to form a diffusion region (11).
(21) A method for manufacturing a semiconductor device, comprising the step of forming (21). (2) The step of forming the diffusion region (21) is a step of forming the diffusion region (21) by the heat treatment and at the same time flattening the surface of the diffusion source layer (20) by the heat treatment. A method for manufacturing a semiconductor device according to claim 1, characterized in that: (3) The substrate (1) is n-type, and the diffusion source layer (10)
Claim 1, characterized in that (20) is SOG (spin on glass) containing p-type impurities.
The method for manufacturing a semiconductor device according to item 1 or 2.