JPH0789562B2 - Element isolation method for integrated circuit - Google Patents

Description

DETAILED DESCRIPTION [Outline] As an element isolation method for an integrated circuit, an element isolation trench buried type is often used in a highly integrated IC. Also in this structure, there is a problem that an inversion layer is generated during operation on the inner surface of the substrate surrounding the element isolation groove to cause element leakage, and a channel cut is usually formed. The present invention describes a method for easily forming a well-characterized channel cut.

[Industrial application field]

The present invention relates to a method of forming a channel cut formed around an element isolation groove of an integrated circuit.

The pn junction isolation method, the oxide film isolation method, the buried element isolation method, etc. are used as the method for isolating each element of an integrated circuit, but the embedded element isolation method is often used for highly integrated ICs. It's being done.

The buried element isolation method is a structure in which a V-shaped cross section or a U-shaped groove perpendicular to the substrate surface is formed in a substrate, and then an oxide film is formed on the inner surface to bury polysilicon.

However, with this structure alone, under the influence of the potential of the wiring layer formed on the upper surface of the separation groove during operation, an inversion layer is generated on the substrate surface in contact with the periphery of the separation groove, and the inversion layer between the electrodes of the same element or the adjacent element Leak current may occur between the electrodes.

To prevent this, a high-concentration impurity layer is formed on the surface of the substrate in contact with a groove called a channel cut or channel stop.

However, when this impurity region is formed by ion implantation, there is a problem that the channel cut cannot be formed uniformly over the entire circumference of the separation groove, and improvement is desired.

[Conventional technology]

A conventional process of forming a channel cut in the U-shaped element isolation groove will be described in detail with reference to FIG.

The oxide film 2 and the nitride film 3 are laminated using the p-type substrate 1.
The oxide film and the nitride film on the isolation groove formation region 4 are removed by etching to form an opening.

A U-shaped groove 5 is formed in the isolation groove formation region by anisotropic etching (RIE method).

Then, boron B is ion-implanted. Ions implanted by ion implantation have a directional property, and in the U-shaped groove 5 having a shape as shown in FIG. 2, most of the ions are implanted in the peripheral region 6 surrounding the bottom surface of the groove, and p ⁺ channel cut 7 is formed after annealing. To be done.

After that, the description of the step of forming the oxide film 8 on the inner surface of the U-shaped groove and burying the polysilicon 9 for planarization is omitted.

[Problems to be solved by the invention]

In the above-described conventional channel cut forming method, the impurity diffusion region is limited to the peripheral region 6 on the bottom surface of the groove.

Therefore, when a wiring portion is formed on the substrate and this integrated circuit is operated, an n-type inversion layer is generated in the peripheral region other than the p ⁺ channel cut 7 of the separation groove, and the n-type inversion layer is formed between the device electrodes or the adjacent device. This causes a problem of generating a leak current.

[Means for solving problems]

The above-mentioned problem is that in the element isolation trench forming step of the integrated circuit, after the isolation trench is formed, the first oxide film is formed on the inner surface of the trench, and SOG containing B ₂ O ₃ is applied to the trench. The step of partially embedding the bottom of the groove and drying, and forming a second oxide film on the inner surface of the groove, applying SOG containing B ₂ O ₃ and P ₂ O ₅ to completely cover the groove. This is solved by an element isolation method for an integrated circuit including a step of burying and drying and a step of forming a p + diffusion region around the groove by heat treatment.

[Action]

The formation of the channel cut impurity region is performed by thermal diffusion of B from SOG containing B ₂ O ₃ filling the isolation trench.

Therefore, the amount of impurities can be easily controlled, and it becomes possible to simultaneously form the channel cut and fill the isolation trench.

Separating the embedding groove by SOG containing the B ₂ O ₃ in two steps, embedding the partial separation trench using a SOG containing first only the _{B 2 O 3, B 2 O} 3 in the next step It is possible to bury it with SOG containing P ₂ O ₅ and P ₂ O ₅ and reduce the etching rate in the subsequent process to facilitate the planarization work.

The method of the present invention also facilitates control of the profile of the channel cut region.

〔Example〕

An embodiment of the present invention will be described in detail with reference to FIG. 1 in comparison with the prior art of FIG.

In FIG. 1, the method up to the step of forming the U-shaped element isolation groove 5 is the same as the method described in the section of the conventional technique.

First, an oxide film 8 of 200 Å is formed on the inner surface of the groove 5 by thermal oxidation.
Form.

Next, in the prior art FIG. ₃ , SOG10 in which B ₂ O ₃ is mixed is applied to completely fill the groove. SOG (Spin On Glass) is R _n
A liquid substance containing Si (OH) _4-n , which is usually used in wafer processing to prevent defects due to hillocks in Al wiring layers.

The coated material is dried and solidified by annealing in N ₂ gas at about 450 ° C. Furthermore, at a temperature of about 950 ° C, N
A channel cut 13 as ap ⁺ diffusion region is formed by annealing in ₂ gas.

In the conventional method shown in FIG. 3, the element isolation trench is buried.
Since SOG containing B ₂ O ₃ has a high etching rate and has a problem in the planarization process, the workability is improved by separating the embedding step into two steps.

This will be described with reference to FIG. After the element isolation groove is formed, SOG10 containing B ₂ O ₃ is applied to partially fill the groove.

The coated material is dried and solidified by annealing in N ₂ gas at about 450 ° C.

Then, again by thermal oxidation, an oxide film 11 of about 300 Å is formed in the upper region where the U-shaped groove is left.

Further, SOG12 in which B ₂ O ₃ and P ₂ O ₅ are mixed is applied, the groove 5 is completely filled, and the same heat treatment as the previous time is performed to solidify.

Through the above steps, by annealing in N ₂ gas at a temperature of about 950 ° C, channel cut as a p ⁺ diffusion region
13 is formed.

〔The invention's effect〕

As explained above, by applying the method for forming a molecular separation groove of the present invention, it is possible to form a p ⁺ channel cut having a desired profile, and the planarization process is improved and the channel cut is improved. Since it is possible to simultaneously form the trenches and bury the isolation trenches, it is a major contribution to reducing the number of steps and improving the quality.

[Brief description of drawings]

FIG. 1 is a sectional view for explaining a method for forming an element isolation groove according to the present invention, and FIGS. 2 and 3 are sectional views for explaining a conventional method for forming an element isolation groove. In the drawing, 1 is a p-type substrate, 2, 8 and 11 are oxide films, 3 is a nitride film, 4 is an isolation groove forming region, 5 is a U-shaped element isolation groove, 6 is a peripheral region of the groove bottom surface, 7, 13 Is a channel cut (p ⁺ diffusion region), 9 is polysilicon, 10 is SOG containing B ₂ O ₃ , and 12 is SOG containing B ₂ O ₃ and P ₂ O ₅ , respectively.

Claims (1)

[Claims] 1. In an element isolation groove forming process of an integrated circuit,
After forming the separation groove (5), a first oxide film (8) is formed on the inner surface of the groove and contains B ₂ O ₃ .
A step of applying SOG (10) to partially bury and dry the bottom of the groove, and forming a second oxide film (11) on the inner surface of the groove to form B ₂ O ₃ and P ₂
An integration characterized by including a step of applying SOG (12) containing O ₅ and completely filling the groove and drying, and a step of forming ap + diffusion region (13) around the groove by heat treatment. Circuit element isolation method.