JPS6037142A - Semiconductor device - Google Patents

Abstract

PURPOSE:To improve characteristics in a fine device in small thickness, particularly, 1mum or less, and to form the semiconductor device having the high density of integration by making impurity concentration in a diffusion layer high in the bottom of a groove and a section in the vicinity of the bottom and low in a section in the vicinity of the surface. CONSTITUTION:B diffusion layers 5 in 5X10<16>cm<-3> concentration are formed to the bottoms of grooves and side surfaces in the vicinity of the bottoms and B diffusion layers 6 in 5X10<15>cm<-3> concentration to sections in the vicinity of the surfaces of the side surfaces in a region 2, which is formed to a Si substrate 1 of a P type (100) face and 10OMEGAcm and to which a device separated by the grooves must be shaped, and the grooves are buried with an insulator 4. Impurity concentration in the vicinity of the surface is made low, and a narrow channel effect is prevented. On the other hand, a device having high impurity concentration has the higher effect of a channel stopper, and the leakage currents of a channel must be brought to 10<-14>A or less per one element. Accordingly, sections in the vicinity of the bottoms of the grooves must be doped in high concentration. The high-concentration impurity layer is useful for improving the performance of a fine device because it is of use for preventing the punch-through of the device.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to an improvement in the isolation structure between semiconductor circuit devices (hereinafter abbreviated as IC).
In order to form so-called channel stoppers on the sides and bottom of a groove formed in a semiconductor substrate of -conductivity type in order to electrically isolate between elements, a conductive layer doped with the same conductivity type as that of the semiconductor substrate. The present invention relates to an IC structure in which the vicinity of the groove bottom is doped with a high concentration, and the vicinity of the semiconductor substrate surface is doped with a low concentration.

[Background of the invention]

Conventional IC isolation between elements is so-called LOCO8 (Lo
cal Oxidation of 5i1icon:
J. A. Abels et al. Phillips Research Report Vol. 25, 118jj 1970; J, A, A
pl) else aA.

philips Res Ropt 25, 118
(1970), ) structure was used for kings, and the main problems with this structure can be summarized as follows.

(υ When forming the oxide film for isolation between elements, the effective width of the pattern is The so-called "bird peak" phenomenon occurs.

The thickness of the thin film that is reduced due to this "bird beak" is generally the same as the thickness of the oxide film used for isolation between devices.

(2) Threshold voltage of oxide film for element isolation (VTR')
In order to maintain a high value and enable electrical isolation between elements, an impurity having the same shape as the substrate is doped as a channel stopper, but this impurity causes lateral diffusion during oxidation, resulting in the so-called " This causes "narrow channel effect". This lateral diffusion progresses up to about 5 times the oxide film thickness, and for example, with an oxide film thickness of 0.5 μm, it is about 2.5 μm on one side, that is, it is affected by the “narrow channel effect” of the 5 μm duck pattern. .

These problems have a significant effect on ICs, especially in sub-μm ICs that use fine #1/cturns of 1 μm or less, and may cause variations in device characteristics of Vra. Therefore, the LOCO8 structure is used. Things are impossible.

The present invention solves the problems of the prior art by forming a groove in a Si substrate, doping the side surfaces of the groove and Jfcm with an impurity that provides the same conductivity type as the Si substrate as a channel stop. The present invention relates to a technique in which the bottom of the groove and the side surfaces near the bottom are doped with 4U at a high concentration, and the side surfaces near the surface are doped with a low concentration. especially,
Coat the glass grooves with an alcoholic solution of silanol,
For example, in the case of 0CD59310 (black market name: manufactured by Tokyo Ohka), by adopting a structure in which it is embedded, the problem in device characteristics, which has been overcome with the prior art, can be eliminated.

[Embodiments of the invention]

The present invention will be specifically described below based on Examples.

Example 1 In this example, the characteristics of a device having an impurity doping distribution according to the present invention will be described as superior to those of a conventional device having a me-J-doping distribution. FIG. 1(a) shows an example of the prior art, in which a groove with a depth of 2/j m and +1 @ 0.8 μm is formed in a P-type (100) plane, 10Ω sub-Si substrate 1. A boron concentration of 3 x 1 with a uniform doping distribution is formed in the region 2 where a 2 μm device is to be formed.
This structure has a channel stopper 3 of 0"cm-" and an insulator 4 deposited to fill the trench.

FIG. 1(b) shows an example of a structure according to the present invention, in which the structure is separated by grooves of 2 μm in depth and 0.8 μm in width formed in a P-type (IOO) surface, 10Ω sub-Si substrate 1. , width 2μm
In the region 2 where a device is to be formed, a B diffusion layer 5 with a roughness of 5 x 10" crn-3 is placed on the bottom of the groove and on the side surfaces near the bottom, and a 5 x 10" roughness layer is placed on the region 2 near the surface of the side surface.
A B diffusion layer 6 with a thickness of cm-3 is formed, and a groove is further formed with an insulator 4.
shows the embedded state.

The results of comparing the electrical characteristics of these two structures, including the conventional LOCO and S structures, are shown in FIG. 2(a). Comparing the dependence of threshold voltage VTII on channel width W, in the conventional LOGO8 structure, when the oxide film thickness is 1 μm (curve 7), W starts from about 10 μm, and when the oxide film thickness is 0.5 μm.
m (curve 8), each VTII starts from about 5 μm.
starts to get high (narrow channel effect). On the other hand, in the conventional trench isolation reconstruction (curve 9), the VTR becomes extremely high from a channel width of about 2 μm.

It can be seen that the horizontal groove separation (curve 10) according to the present invention exhibits a short VrIIk up to a channel width of 1 μm, and is an indispensable method for realizing a sub-μm device.

The reason why the narrow channel effect of the device according to the present invention as in this example is small is that the impurity concentration near the surface of the groove side surface (about 5 x I 015 cm-") is due to the impurity concentration (about 1 x 1016 cm-") due to channel doping. ) is also low, so the formation of an inversion layer that occurs when a bias is applied to the gate depends only on the impurity due to channel doping.In other words, the VTR has a work function ΦM
B, interface level Q88, Fermi potential φt1 gate valley imaginary C08, substrate resonant concentration Nm↓, and substrate bias VIB are increased by the following equation.

Here, K is a constant that affects the dielectric constant of the oxide film. Therefore, the change in threshold voltage ΔVTH is proportional to NAl/2, and increases as the number of 8 people increases. The narrow channel effect can be said to be a phenomenon in which N is greater than the channel impurity concentration. Therefore, as in the present invention, by reducing the concentration of non-Stt substances near the surface, the narrow channel effect can be prevented.

On the other hand, the effect of a channel stopper is large when the impurity concentration is localized, and the channel leakage current is also reduced per unit.
``4A or less.For this reason, it is safe to apply a high concentration of dope near the paper part of the groove.Reed, this impurity layer prevents punch-through of the device. Figure 2(b) shows the results of comparing the punch-through breakdown voltage of the structure of the present invention with the conventional structure.
In this case, the punch-through breakdown voltage decreases to about 2 V with a channel length of 1 μm, but in the device 10a according to the present invention, the punch-through breakdown voltage decreases to about 5 V.
is greatly improved.

Example 2 In this example, an example of impurity doping using coated glass will be described.

FIG. 3(a) shows a photolithography and drying process in which a groove of 0.8 μm in width and 3 μm in depth is formed in a P-type (100-square-face, 10-ohm pattern) Si substrate 11 so as to surround the area where devices such as transistors are to be formed. P was formed using etch technology, and further oxidized in a 1000t:' dry acid XW atmosphere to a thickness of 20%.
This shows the state in which oxidation of 12 nm is formed. Figure 3 (b
) is coated glass, 0CD59310 (product name:
(manufactured by Tokyo Ohka) at a rotational speed of 5000 r-, then
After baking in a 50C atmosphere to evaporate the solvent and form an embedded layer 13, 0CD59210 (trade name: manufactured by Tokyo Ohka) was again applied by spin coating at 5,000 mm.
0t;' This shows the state in which the embedded shield 14 containing low impurities was formed by baking in a dry solution for 20 minutes. These head cloths
The baking process can be repeated several times. Figure 3 (C)
The above semiconductor substrate was heated for 30 minutes in a nitrogen* atmosphere at 1000C.
After annealing for 1 minute, a high concentration B diffusion layer (approximately 5
x 10" cm-3) 15 and a low grade B forgiveness layer near the substrate surface (approximately 5 x 10" cm-3) 16
This shows the state in which it has been formed.

In the structure shown in this example, a thermal oxide film is formed to stabilize the Sl/8102 structure, but this is not necessarily essential. In addition, by covering the surface of the semiconductor substrate other than the grooves with a thickened silicon film (Si3N4) and annealing the buried layer of the coated glass in a wet oxidation atmosphere, the diffusion of B can be accelerated and It is also possible to increase the depth.

Example 3 In this example, a method of doping B using ion implantation method will be described. Figure 4(a) shows the P-type (ioo) surface 1
A thermal oxide film with a thickness of 2Q nm (
Si02)17 and CVD(1(C11einlC4
1VBpBV 1) epO8itlon method) A silicon nitride film (S'3N4) 18 with a thickness of 12Qnm is formed respectively, and a groove with a width of 1μm and a depth of 4μm is formed using conventional photolithography and dry etching techniques. After that, hR life ion is implanted by ion implantation.
o13z-" is implanted, and a B+ implant shield 19 is formed. At this time, B+ ions are implanted mainly into the bottom of the groove and the inclined side surfaces near the paper surface, and the B+ ions are implanted into the cloth plate, which has a nearly vertical shape. It is almost never driven into the sides of the groove in the vicinity.

FIG. 4(b) shows a state where an 81 substrate was oxidized in dry oxygen to form 810220 with a thickness of 5 Q nm, and 810221 with a thickness of 0.6 A m(7) was deposited by a low pressure CVD method. During the deposition of 810221, the trenches formed in the Si substrate were completely filled, and the B ion implantation chamber 19 was annealed to form 7X10'6cn1-3.
At a high concentration, debris is formed near the bottom with a junction depth of approximately 2 μm and near the surface with a junction depth of 0.5 μm 1 # degree 5 × 10”tM−3. Figure 4 (C) shows The CVD8
i0a layer 21, 5jsN<layer 18. The S-02 layer F is etched to expose the Si substrate in the region where a device is to be formed. By creating a device on a substrate, as shown in Example 1, a device with better characteristics than the conventional technology could be realized.

In this example, the grooves were filled with 7'cSiOg deposited by the CVD method, but it is also possible to fill the grooves with coated glass in the same manner as in Example 2. Also, B+ due to ion implantation
During ion implantation, it is also possible to dope the wall by changing the implantation angle. Since ions have a strong straight propagation property, they are implanted obliquely in the 1i+Il wall group, so that the penetration depth into the substrate is not shallow, which is advantageous in implementing the present invention.

〔Effect of the invention〕

As is clear from the above embodiments, according to the present invention, especially 1μ
It is possible to improve the physical properties of devices with a thickness of less than m, making it extremely useful for forming semiconductor devices with high product density.

[Brief explanation of drawings]

FIG. 1(a) is a cross-sectional view showing the conventional structure, FIG. 2 is a curve diagram comparing the characteristics of the conventional structure and the present invention, and FIG. 1(b), FIG. 3, and FIG. FIG. 1.11... Silicon substrate, 2... Device formation region, 3.5, 6, 15, 16.19... Boron diffusion layer, 4.13.14.21... Buried insulator, 12゜Tomi 1 figure (ri 1st figure (b) ¥7:J z figure (Kunishi zrw (b) 7 ``Y1-year-old L-L (Pmt 3rd figure (L) banquet 3 figure (b) no. Figure 3 (Fig. 4 (phantom)

Claims (1)

[Claims] 13- A silicon single crystal substrate having a conductivity type, a groove formed in the substrate, and an impurity that gives a first conductivity type to the 0111 plane and the bottom surface of the line groove to function as a channel stopper. What is claimed is: 1. A semiconductor device having a structure comprising a diffusion layer, characterized in that the impurity rs degree of the diffusion layer is low at and near the trench bottom and low near the surface. 2. The impurity ambiguity of the diffusion layer is at least close to six sides,
2. The semiconductor device according to claim 1, wherein the concentration of channel doping is also lower. 3. The semiconductor device according to claim 1 or 2, wherein the line groove is filled with an insulator.