JPH03257947A - Formation and isolation method for element - Google Patents

Abstract

PURPOSE:To enable batch processing and heighten throughput more than the processing by ion implantation by burying the groove in an isolating region formed in a semiconductor substrate with a solid layer containing impurities, and then by solid-phase-diffusing the impurities into the semiconductor substrate just under the groove from the solid layer by heat treatment and forming an impurity region. CONSTITUTION:A silicon oxide film 10 is deposited on a silicon substrate 9, and a silicon nitride film 11 is deposited on it by reduced-pressure CVD. And a window 13 is provided in an isolating region by photolithography. Besides a groove 14 is made by dry etching. Next an oxide film 15 is grown on the surface of the silicon substrate 9. Only the oxide film 15 at the bottom of the groove 14 is removed by dry etching. And a silicon oxide film 16 containing boron is deposited by the reduced-pressure CVD. After the flattening of the BSG film 16, an element 18 is formed in an element forming region by a usual phanar process. At the time, a P-type high-density impurity region 19 is formed by heat treatment in the usual planar process.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming an isolation region.

BACKGROUND OF THE INVENTION In recent years, integrated circuit technology that incorporates a large number of functional elements on a single semiconductor substrate has been developed. Local oxidation of LO is a means to promote high density in such integrated circuits.
GOS (Loca J○xidation of S 1l
icon) There is a law.

With the miniaturization of devices, the LOCO3 method reduces the LOG during oxidation.
It is becoming impossible to ignore the bird's beak of the O3 film and the diffusion directly under the LOGO5 film due to heat. Bird's beak can be improved by changing the method of forming the LOGO8 film and the separation structure. Here, a groove isolation method having a structure similar to LOGO5 isolation will be described.

FIG. 5 shows a process sectional view of the BOX separation method, which is a conventional groove separation method.

A silicon oxide (Sigh) film 2 and a silicon nitride (Si3N4) film 3 as an oxidation-resistant material are deposited on a silicon substrate 1, and isolation regions 4 are formed at predetermined portions by photolithography and etching (FIG. 5(a)). .

Next, grooves 5 are formed in the isolation region 4 by dry etching,
Ion implantation is performed over the entire surface of the silicon substrate 1 to form a high concentration impurity region 6 called a channel stopper in the silicon substrate 1 directly under the trench 5 (FIG. 5(b)).

After that, after removing the silicon nitride II 3 and the silicon oxide film 2, a silicon oxide film 7 is deposited on the entire surface of the silicon substrate, the trenches 5 are filled, and a resist 8 is further applied on the silicon oxide film 7 to flatten the surface. (Figure 5 (C)).

Next, the area of the groove 5 is flattened by etching back by dry etching (FIG. 5(d)).

Problems to be Solved by the Invention In trench isolation, the formation of the high-concentration impurity region 6, which serves as a channel stopper directly under the trench 5, is performed by ion implantation, resulting in a low throughput, and also requires heat treatment at high temperatures to activate the impurities. As a result, impurities diffuse into the element region, resulting in a lower isolation voltage and a narrow channel effect that deteriorates device characteristics as the element region becomes smaller.

Further, in heat treatment, outward diffusion of impurities occurs, resulting in a desired impurity concentration, particularly <<, and variations in impurity distribution. In ion implantation, the impurity implantation region changes depending on the shape of the trench 5, so it is necessary to accurately control the shape of the trench 5. Furthermore, the ion implantation during the formation of the high concentration impurity region 6 is also implanted into the element formation region, thereby degrading the element characteristics and complicating the element formation process after isolation formation.

Means for Solving the Problems The present invention has been made to solve the above problems, and is a method in which an impurity region is formed by a solid diffusion layer made of a solid layer, and a trench is filled with the solid layer.

Batch processing using a diffusion furnace can be used to form the high concentration impurity region immediately below the working groove. Further, high concentration impurity regions can be selectively formed by dry etching. Impurities are supplied by solid-phase diffusion using solids, and a constant concentration of impurities can always be supplied from a diffusion source.

As the source of impurities, silicon oxide or spin-coated glass containing impurities can be used.

Embodiment FIG. 1 is a cross-sectional view showing the element isolation forming process according to an embodiment of the present invention, and an example will be described in which it is used for isolation when integrating N-channel MO8) transistors. Silicon substrate 9
A P-type silicon wafer was used. A silicon oxide film 10 is deposited on a silicon substrate 1, and a silicon nitride film 11 is deposited thereon using low pressure CVD. A resist pattern 12 is formed in areas other than the isolation region using photolithography, and the silicon nitride film 11 is formed using the resist pattern 12 as a mask.
Then, the silicon oxide film 10 is removed by reactive ion etching, and a window 13 is opened in the isolation region (FIG. 1(a)). Thereafter, the silicon substrate 1 is dry-etched into a desired shape using the resist pattern 12, the silicon nitride film 11, and the silicon oxide film 10 as masks, thereby forming the grooves 14. The width of the groove 14 was 1 μm, and the depth of the groove 14 was 0.5 μm (FIG. 1(b)).

Next, after removing the resist pattern 12, silicon nitride film 11 and silicon oxide film 10,
An oxide film 15 is formed on the surface of the silicon substrate 1 for 20 minutes using VD.
Grow 0A. After this, groove 1 is etched using dry etching.
Etching is performed to remove only the oxide film 15 at the bottom of the wafer 4. Thereafter, a silicon oxide film (hereinafter referred to as BSG film) 16 containing 10 wt% boron is deposited at 800 OA using low pressure CVD. After this, a resist 17 is applied to a thickness of 2 μm over the entire surface of the silicon substrate 1, and the silicon substrate 1 (FIG. 1(C)).Next, dry etching is performed under conditions such that the etching rates of the resist 17 and the BSG film 16 are equal, and the BSG film 16 is flattened (FIG. 1(C)). (d)).

Thereafter, the element 18 is formed in the element forming region using a normal planar process. At this time, P-type high concentration impurity region 19 is formed by heat treatment during the normal planar process.
is formed (Fig. 1(e)).

FIG. 2 shows the narrow channel effect of BOX isolation in which a high concentration impurity region (channel stopper) 6 or 19 is formed by the conventional ion implantation method and the device isolation formation method of the present invention.

The horizontal axis represents the channel width, and the vertical axis represents the threshold voltage.

It can be seen from FIG. 2 that the narrow channel effect is smaller in the device isolation formation method of the present invention than in the conventional ion implantation method.

FIG. 3(a) shows the circuit configuration when measuring withstand voltage.

FIG. 3(b) shows B in which a high concentration impurity region 6 or 19 is formed by the conventional ion implantation method and the element isolation formation method of the present invention.
The relationship between the distance between junctions of OX isolation and withstand voltage is shown.

It can be seen from FIG. 3 that sufficient breakdown voltage can be obtained even if the element dimensions are made smaller by the element isolation forming method of the present invention than by the conventional ion implantation method.

In the conventional ion implantation method, the impurity concentration changes due to outward diffusion and its distribution varies, but in the device isolation formation method of the present invention, a constant impurity concentration is always obtained even during the heat treatment after the isolation step, and the impurity distribution also changes according to the complementary error function. It becomes a distribution of shapes.

FIG. 4 shows the relationship between the impurity concentration and the distance in the depth direction of the silicon substrate 9 from the BSGS upper film.

The parameters indicate the heat treatment time at 900° C. after deposition of the BSGS top film.

The impurity implantation region is related to the controllability of the window forming process of the silicon oxide film 15 deposited after the trench 14 is formed, and this etching can be easily accomplished by using dry etching. Therefore, there is no need to control the shape of the groove 14.

Furthermore, since ion implantation is not performed, impurities do not enter the element region and deteriorate the element characteristics, and the element formation process after isolation formation does not become complicated.

Here, a BSGS top film was used as an impurity source, but
Rotating tube cloth glass containing boron (usually SOG: 5 pins)
-On Glass) eliminates the need to use CVD, further simplifying the process.

Furthermore, when forming a P-channel transistor, a silicon oxide film (PSG) containing phosphorus is used.

BPSG), rotating frozen cloth glass can be used.

Effects of the Invention In the element isolation forming method of the present invention, a high concentration impurity region (channel stopper) under the trench surface is formed using impurities in the oxide film during trench filling as a supply source, so batch processing is possible and it is performed by ion implantation. It has a higher throughput than the case.

Further, activation of impurities is caused by solid-phase diffusion, so that the impurities are sufficiently diffused by heat treatment after the separation step. In addition, since the lateral diffusion of impurities can be prevented by the oxide film on the trench sidewalls, the impurities can diffuse into the element region, lowering the isolation breakdown voltage.
No narrow channel effects occur.

[Brief explanation of drawings]

FIGS. 1(a) to (e) are process cross-sectional views showing a device isolation forming method in an embodiment of the present invention, and FIG. 2 is a characteristic showing a narrow channel effect by the device isolation forming method in an embodiment of the present invention. 3(a) is a diagram showing a circuit configuration for measuring the relationship between junction distance and breakdown voltage in an element, and FIG. A characteristic diagram showing the relationship between junction distance and breakdown voltage, FIG. 4 is an impurity distribution diagram directly under the isolation region according to the device isolation formation method in one embodiment of the present invention, and FIG. 5 is a process diagram showing the conventional device isolation formation method. FIG. 1.19...Silicon substrate, 2,7.10...
...Silicon oxide film, 3.11...Silicon nitride film, 4...Isolation region, 5,14...
... Groove, 6, 19... High concentration impurity region, 8,
17...Resist, 12...Resist pattern, 13...Window, 15...Oxide film, 16...BSG film, 18... ·····element.

Claims (1)

[Claims] forming a groove as an isolation region in a semiconductor substrate; burying the groove with a solid layer containing an impurity; solid-phase diffusion of the impurity from the solid layer into the semiconductor substrate directly under the groove by heat treatment; 1. A method for forming element isolation, comprising a step of forming.