KR960014447B1 - Method of isolation of a semiconductor device - Google Patents

Method of isolation of a semiconductor device Download PDF

Info

Publication number
KR960014447B1
KR960014447B1 KR1019930026303A KR930026303A KR960014447B1 KR 960014447 B1 KR960014447 B1 KR 960014447B1 KR 1019930026303 A KR1019930026303 A KR 1019930026303A KR 930026303 A KR930026303 A KR 930026303A KR 960014447 B1 KR960014447 B1 KR 960014447B1
Authority
KR
South Korea
Prior art keywords
oxide film
trench
film
mask
forming
Prior art date
Application number
KR1019930026303A
Other languages
Korean (ko)
Other versions
KR950021349A (en
Inventor
한태현
이수민
조덕호
염병렬
권오준
Original Assignee
재단법인 한국전자통신연구소
양승택
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 재단법인 한국전자통신연구소, 양승택 filed Critical 재단법인 한국전자통신연구소
Priority to KR1019930026303A priority Critical patent/KR960014447B1/en
Publication of KR950021349A publication Critical patent/KR950021349A/en
Application granted granted Critical
Publication of KR960014447B1 publication Critical patent/KR960014447B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)

Abstract

(A) removing a LPCVD oxide film(5), a nitrided film(4) and an oxide film(3) on a region(6); (B) forming a trench by etching a substrate on the region(6) selectively, and forming a first oxide film(8) on the trench; (C) forming a mask oxide film(10) by etching the LPCVD oxide film(5); (D) forming a second oxide film(11); (E) removing the second oxide film(11) on the bottom(12) of the trench and the exposed nitrided film(4) of a region(14); (F) grounding the substrate by forming p+ region(16) after filling the trench with Boron-doped polysilicone(15); (G) obtaining a wafer surface(17) of flattening polysilicone by etching the oxide film(13) on the nitrided film(4); (H) defining an active region by using a photoresist film(18); (I) forming an thermal oxide film(20) by etching the exposed nitrided film(4).

Description

준자기정렬 트렌치 소자격리방법Quasi-magnetic alignment trench isolation method

제1도는 종래에 트렌치 소자격리 단면도.1 is a conventional trench isolation view.

제2도는 본 발명에 따른 트렌치 소자격리 단면도.2 is a trench isolation view in accordance with the present invention.

제3도는 상기 제2도에 따른 트렌치 소자격리의 제조 공정도.3 is a manufacturing process diagram of a trench device isolation according to FIG.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : n+매몰층 2 : n-에피층1: n + buried layer 2: n- epi layer

3.13 : 산화막 4,19 : 질화막3.13: oxide film 4,19: nitride film

5 : LPCVD 산화막 8 : 제1산화막5: LPCVD oxide film 8: First oxide film

10 : 마스크용 산화막 11 : 제2산화막10 oxide film for mask 11 second oxide film

15,17 : 다결정실리콘 16 : p+영역15,17 polysilicon 16: p + region

18 : 감광막 20 : 열산화막18: photosensitive film 20: thermal oxide film

본 발명은 고속 정보처리 시스템에서 바이폴라 소자 및 BiCMOS 공정기술에 이용될 수 있는 준자기정렬트렌치 소자 격리 방법에 관한 것이다.The present invention relates to a quasi-magnetic alignment trench device isolation method that can be used in bipolar devices and BiCMOS process technology in high-speed information processing systems.

일반적으로, 반도체 장비 및 공정기술의 급성장으로 바이폴라소자의수평, 수직방향으로의 크기가 축소되어 소자의 동작 속도 뿐만아니라 집적도도 크게 향상되고 있다.In general, due to the rapid growth of semiconductor equipment and process technology, the size of the bipolar device is reduced in the horizontal and vertical directions, thereby greatly improving the integration speed as well as the operation speed of the device.

이러한 소자면적의 크기를 축소하기 위해서 다결정실리콘 자기정렬기술 및 트렌치 소자격리 기술등 공정기술의 향상에 기반을 두고 있으며, 반도체 소자가 점차적으로 고집적화됨에 따라 소자격리와 소자간의 배선이 더욱 중요한 문제가 되고 있다.In order to reduce the size of the device area, it is based on the improvement of process technology such as polysilicon self-alignment technology and trench device isolation technology. As the semiconductor devices are gradually integrated, device isolation and interconnection between devices become more important problems. have.

따라서, 종래에는 바이폴라 및 BiCMOS 공정에 사용되고 있는 트렌치 소자격리 기술이 제1도에서 나타낸 바와같이 구성되었는데, 이것은 트렌치 마스크(3)와 화설영역정의 마스크(4) 사이에 일정한 간격(1)이 생겨서 콜렉터와 p-기판간의 기생 접합용량의 증가를 초래하는 문제점이 발생되었다.Therefore, the trench isolation method conventionally used in bipolar and BiCMOS processes is constructed as shown in FIG. 1, which has a constant spacing (1) between the trench mask (3) and the snow area defining mask (4). There was a problem that caused an increase in the parasitic junction capacity between the p-substrate and the p-substrate.

상기 문제점을 해결하기 위하여 본 발명은 종래의 트렌치 소자격리 기술을 수정보완하여 콜렉터와 기판 사이의 기생접합용량을 감소시켜 칩의 집적도 및 동작속도의 향상을 제공하는데 목적이 있다.In order to solve the above problems, an object of the present invention is to provide an improvement in chip integration and operating speed by reducing the parasitic capacitance between the collector and the substrate by completing the conventional trench device isolation technology.

상기 목적을 달성하기 위하여 본 발명에서는 첨부된 도면에 의거 상세한 설명을 한다.In the present invention to achieve the above object will be described in detail based on the accompanying drawings.

먼저, 제2도는 본 발명에 따른 트렌치 소자격리 단면도를 나타낸다.First, FIG. 2 shows a trench isolation view in accordance with the present invention.

다결정실리콘과 질화막사이의 선택적인 연마(selective polishing) 방법으로 트렌치를 채우기 위해 적충한 다력정 실리콘(6')을 연마하고 마스크층인 질화막(5')을 활성영역 정의시 산화방지용 마스크층으로 다시 사용함으로써 트렌치 마스크(3')와 활성영역 정의 마스크(4') 사이의 간격을 최소화 하여(제2도의 1') 콜렉터와 기판사이의 면적(2')을 감소시켜 집적도 향상을 꼬하였다.Selective polishing method between the polysilicon and the nitride film is used to grind the appropriate polysilicon silicon 6 'to fill the trench, and the nitride film 5', which is a mask layer, is again used as an anti-oxidation mask layer when defining the active region. By using this method, the gap between the trench mask 3 'and the active region defining mask 4' was minimized (1 'in FIG. 2) to reduce the area 2' between the collector and the substrate, thereby improving integration.

상기 제2도에 대한 제조공정의 순서를 제3도(A)~(I)와 같이 나타내어 상세히 설명한다. p-형 실리콘 기판의 전면에 비소(arsenic)를 이온주입하고 열처리하여 n+매몰층(1)을 형성하고 원하는 두께의 인(phosphorus)이 첨가된 n-에피층(2)을 형성한다.The procedure of the manufacturing process with respect to FIG. 2 is shown as FIG. 3 (A)-(I), and it demonstrates in detail. Arsenic (ions) are ion-implanted on the entire surface of the p-type silicon substrate and heat treated to form an n + buried layer 1, and an n- epi layer 2 to which phosphorus (phosphorus) of a desired thickness is added is formed.

상기 n-에피층(2) 상면에 400A 두께의 산화막(3), 1200A의 질화막(4) 및 8000A 두께의 LPCVD(Low Pressure Chemical Vapor Deposition) 산화막(5)을 도포(deposition)한 다음 도면부호 6부분을 제외한 나머지 부분을 감광막(photo resist)으로 마스킹한 다음 상기 도면부호 6부분의 LPCVD 산화막(5), 질화막(4), 산화막(3)을 차례로 건식식각하고 감광막을 제거하여 (A)제조공정을 완성한다.A 400A thick oxide film 3, a 1200A nitride film 4, and a 8000A low pressure chemical vapor deposition (LPCVD) oxide film 5 were deposited on the n-epitaxial layer 2, and then, reference numeral 6 After masking the remaining portion except the portion with a photoresist, dry etching the LPCVD oxide film 5, the nitride film 4, and the oxide film 3 in 6 parts of the reference numerals in turn, and removing the photoresist film (A) To complete.

LPCVD 산화막(5)을 마스크층으로 하여 노출된 실리콘을 선택적으로 건식식각하여 트렌치를 만든 후, 건식식각에 의한 손상을 완화시키기 위하여 트렌치의 측면 및 바닥위에 얇은 제1산화막(8)을 형성시켜 (B)제조공정을 완성한다.After using the LPCVD oxide film 5 as a mask layer to selectively dry-etch the exposed silicon to form a trench, a thin first oxide film 8 is formed on the side and bottom of the trench to mitigate damage caused by dry etching ( B) Complete the manufacturing process.

다음은 상기 트렌치내에 형성된 제1산화막(8)을 습십식각 방법으로 제거한다.Next, the first oxide film 8 formed in the trench is removed by a wet etching method.

이때, 상기 웨이퍼 표면의 LPCVD 산화막(5)을 동시에 원하는 만큼 식각하여 도면부호 9부분의 산화막을 제거하고, 마스크용 산화막(10)을 남게하여 (C)제조공정을 완성한다. 상기 도면부호 9부분의 산화막을 제거한 이유는 상기 제2도의 트렌치 마스크(3')와 활성영역정의 마스크(4') 사이의 정렬오차(misalign)를 보상하기 위한 것으로 산화막의 습식 식각율을 이용하여 원하는 두께를 식각하여 한다.At this time, the LPCVD oxide film 5 on the wafer surface is simultaneously etched as desired to remove the oxide film at 9 parts, leaving the mask oxide film 10 to complete the manufacturing process (C). The reason for removing the oxide layer 9 is to compensate for misalignment between the trench mask 3 'and the active region defining mask 4' of FIG. 2 by using a wet etching rate of the oxide layer. Etch the desired thickness.

또한, 상기 질화막(4)위의 마스크용 산화막(10)은 이후 트렌치의 측면산화막형성 공정과 다결정실리콘의 연마공정시 질화막(4)을 보호할 수 있도록 충분히 두꺼워야 한다.In addition, the oxide film 10 for the mask on the nitride film 4 should be thick enough to protect the nitride film 4 during the laterally forming the side oxide film of the trench and the polishing process of the polysilicon.

트렌치 측면산화막을 형성하기 위하여 1500A 두께의 제2산화막(11)을 형성하는데, 이때 상기 트렌치 마스크용 산화막(10)은 트랜치내에 형성된 제2산화막(11)보다 상대적으로 두껍도록 (D)제조공정을 완성한다.In order to form a trench side oxide film, a second oxide film 11 having a thickness of 1500 A is formed, wherein the oxide film for trench mask 10 is relatively thicker than the second oxide film 11 formed in the trench (D). Complete

다음은, 산화막과 질화막의 식각선택비를 비슷하게 하여 건식식각방법으로 상기 트렌치 바닥 상면의 제2산화막(11)과 노출된 상기 질화막(4)을 제거하여 도면부호 14부분과 같이 형성하는 (E)제조공정을 완성한다.Next, by removing the second oxide film 11 and the exposed nitride film 4 of the upper surface of the trench bottom by a dry etching method by making the etching selectivity of the oxide film and the nitride film similar to (E) Complete the manufacturing process.

한편, 상기 트렌치 바닥(12)의 상기 제2산화막(11)을 건식식각한 후 질화막(4)위의 산화막(13)이 남아 있어야 하며, 이 산화막(13)은 다결정실리콘을 연마할 때 상기 질화막(4)을 보호하는 마스크층 역할을 한다.On the other hand, after dry etching the second oxide film 11 of the trench bottom 12, an oxide film 13 on the nitride film 4 must remain, and the oxide film 13 is used to polish the polycrystalline silicon. (4) serves as a mask layer to protect.

상기 트렌치를 붕소(Boron)가 도핑(doping)된 다결정실리콘(15)으로 채운 후 열처리를 하여 기판으로 붕소가 확산되게 하여 실리콘층에 p+영역(16)을 형성하여 기판접지 공정인 (F)공정을 완성한다.Filling the trench with boron-doped polysilicon 15 and heat-treating the boron to diffuse into the substrate to form a p + region 16 in the silicon layer to form a substrate grounding process (F). To complete.

상기 산화막(13)이 노출될때까지 다결정실리콘(15)을 기계 화학적 염마방법(denial mechanical pelishing)으로 연마한 다음 노출된 산화막(13)을 습식식각하고, 상기 다결정실리콘(15)이 채워진 부분의 다결정실리콘(17)을 질화막(4)이 손상되지 않도록 높은 선택비를 갖는 기계화학적 연마방법으로 제거하여 (G)제조공정을 완성한다.The polysilicon 15 is polished by mechanical mechanical pelishing until the oxide film 13 is exposed, and then the exposed oxide film 13 is wet etched, and the polycrystal of the portion filled with the polysilicon 15 is exposed. The silicon 17 is removed by a mechanical chemical polishing method having a high selectivity so that the nitride film 4 is not damaged, thereby completing the manufacturing process (G).

여기서 질화막(4)은 활성영역정의시 산화방지용 마스크층으로 이용된다. 상기 (G)제조공정과 같이 완성된 기판에 감광막(18)을 사용하여 소자가 형성되는 활성영역을 정의하여 (H)공정을 완성한다.The nitride film 4 is used as an anti-oxidation mask layer when defining the active region. A process (H) is completed by defining an active region in which a device is formed using the photosensitive film 18 on the completed substrate as in the manufacturing process (G).

이때, 트렌치 정의용 마스크가 패턴의 한쪽 끝이 트렌치 중앙에 놓이도록 형성한다.At this time, the trench defining mask is formed so that one end of the pattern is placed in the center of the trench.

상기 (H)제조공정과 같이 기계화학적인 연마(CMP)에 의한 평탄화 웨이퍼 표면 특히, 상기 다결정실리콘(17)의 트렌치 부분이 평탄하게 되여 마스크 정렬오차를 줄일 수 있으며, 정렬오차에 의한 수율감소를 줄이기 위하여 트렌치 윗부분을 산화막 습식식각방법에 의하여 넓혀 주었다.As in the (H) manufacturing process, the surface of the planarized wafer by mechanical chemical polishing (CMP), in particular, the trench portion of the polysilicon 17 is flattened to reduce the mask alignment error and to reduce the yield due to the alignment error. In order to reduce, the upper part of the trench was widened by an oxide wet etching method.

상기 감광막을 사용한 마스크 공정 후 노출된 질화막(4)을 건식식각한 다음 상기 감광막(18)을 제거하고, 남은 질화막(19)을 마스크층으로 열산화막(20)을 형성시켜 (I)공정을 완성한다.After etching the exposed nitride film 4 after the masking process using the photoresist film, the photoresist film 18 is removed, and the thermal nitride film 20 is formed using the remaining nitride film 19 as a mask layer to complete step (I). do.

이후 소자 제조공정은 종래의 다결정실리콘 자기정렬방법의 바이포라 및 BiCMOS 제조공정을 따른다.Afterwards, the device fabrication process follows the bipolar and BiCMOS fabrication processes of the conventional polysilicon self-alignment method.

이상과 같은 본 발명은 트렌치와 활성영역 사이의 면적을 줄임으로써 집적도 향상과 기샐접합용량의 감소에 의한 동작속도의 향상이 기대되는 이점이 있다.The present invention as described above has the advantage that the reduction in the area between the trench and the active region is expected to improve the integration speed and the operation speed by the reduction of the vapor junction capacity.

Claims (4)

p형 기판위에 n+매몰층(3)을 형성하고, 이 위에 n-에피층(2)을 형성한 위에 소정 두께의 산화막(3), 질화막(4), LPCVD 산화막(5)순으로 적충한 후 소정부분(6)을 제외한 나머지 부분을 마스킹한 다음, 상기 소정 부분(6)의 상기 LPCVD 산화막(5), 질화막(4), 산화막(3)을 제거하는 공정(A)과, 상기 소정부분(6)에서의 기판을 선택적으로 식각하여 트렌치를 만든 후, 식각에 의한 손상을 완화시키기 위해서 상기 트렌치면에 제1산화막(8)을 형성하는 공정(B)과, 상기 제1산화막(8)을 소정 식각법에 의하여 제거한 후 상기 LPCVD 산화막(5)을 원하는 두께만큼 식각하여 마스크용 산화막(10)을 형성하고, 소정부분(9)의 상기 산화막(3, 10)을 트랜치 마스크와 활성영역정의 마스크 사이의 정렬오차를 보상하기 위해서 제거하는 공정(C)과, 상기 트렌치 측면 산화막을 형성하기 위하여 소정 두께의 제2산화막(11)을 형성하는 공정(D)과, 상기 트렌치 바닥부분(12)의 상기 제2산화막(11)과 소정 부분(14)의 노출된 질화막(4)을 제거하고, 마스크층 역할을 하는 산화막(13)을 남게하는 공정(E)과, 상기 트렌치를 소정 원자가 도핑된 다결정실리콘(15)으로 채운 후, 열처리를 하여 상기 기판으로 상기 소정원자가 확산되게 하여 p+영역(16)을 형성하여 기판을 접지하는 공정(F)과, 상기 다결정실리콘(15)을 기계화학적 연마방법에 의해서 상기 산화막(13)이 노출될때까지 연마한 다음 상기 질화막(4)위의 산화막(13)을 식각하여 평탄화 다결정실리콘의 웨이퍼표면(17)을 얻는 공정(G)과, 상기 웨이퍼표면(17)위에 감광막(18)을 사용하여 활성역역을 정의하고, 이 감광막(18)의 패턴의 한쪽 끝이 트렌치 중앙 위에 형성되게 하여 트렌치 정의용 마스크로서 이용되는 공정(H)과, 상기 감광막(18)을 사용한 마스크 공정 후 상기 노출된 질화막(4)을 식각하고 감광막(18)을 제거하고, 남은 질화막(19)을 마스크층으로 하여 열산화막(20)을 형성하는 공정(I)을 포함하는 준자기정렬 트렌치 소자 격리방법.After the n + buried layer 3 is formed on the p-type substrate, and the n-epitaxial layer 2 is formed thereon, an oxide film 3, a nitride film 4, and an LPCVD oxide film 5 having a predetermined thickness are deposited in this order. Masking the remaining portions except the predetermined portion 6, and then removing the LPCVD oxide film 5, the nitride film 4, and the oxide film 3 of the predetermined portion 6, and the predetermined portion ( After selectively etching the substrate in 6) to form a trench, the step (B) of forming the first oxide film 8 on the trench surface in order to alleviate the damage caused by etching, and the first oxide film 8 After removal by a predetermined etching method, the LPCVD oxide film 5 is etched to a desired thickness to form a mask oxide film 10, and the oxide films 3 and 10 of a predetermined portion 9 are trench masks and active area defining masks. A step (C) for removing to compensate for misalignment therebetween, and a small amount for forming the trench side oxide film. Forming a second oxide film 11 having a predetermined thickness, removing the second oxide film 11 of the trench bottom portion 12 and the exposed nitride film 4 of the predetermined portion 14, A step (E) of leaving the oxide layer 13 serving as a mask layer, and filling the trench with polycrystalline silicon 15 doped with a predetermined atom, followed by heat treatment to diffuse the predetermined atom onto the substrate to form a p + region 16. ) And grounding the substrate, and polishing the polycrystalline silicon 15 until the oxide film 13 is exposed by a mechanical chemical polishing method, followed by the oxide film 13 on the nitride film 4. Etching to obtain the wafer surface 17 of the planarized polysilicon, and defining an active region using the photosensitive film 18 on the wafer surface 17, and one end of the pattern of the photosensitive film 18 A ball to be formed on the center of the trench and used as a mask for defining the trench After the mask process using the positive electrode (H) and the photosensitive film 18, the exposed nitride film 4 is etched, the photosensitive film 18 is removed, and the thermal oxide film 20 is formed using the remaining nitride film 19 as a mask layer. A quasi-magnetic alignment trench device isolation method comprising the step (I) of forming. 제1항에 있어서, 상기 마스크용 산화막(10)은 상기 제2산화막(11)보다 상대적으로 두께가 두껍게 형성되는 것을 특징으로 하는 준자기정렬 트렌치 소자격리방법.The quasi-magnetic alignment trench isolation method according to claim 1, wherein the mask oxide film (10) is formed to be relatively thicker than the second oxide film (11). 제2항에 있어서, 상기 공정(G)의 질화막(4)은 활성영역정의시 산화방지용 마스크층으로 이용되는 것을 특징으로 하는 준자기정렬 트렌치 소자격리방법.The quasi-magnetic alignment trench isolation method according to claim 2, wherein the nitride film (4) of the step (G) is used as an anti-oxidation mask layer when defining an active region. 제1항에 있어서, 상기 공정(B)의 산화막(5)을 습식식각하여 공정(C)의 (P)를 형성시키는 것을 특징으로 하는 준자기정렬 트렌치 소자격리방법.The quasi-magnetic alignment trench isolation method according to claim 1, wherein the oxide film (5) of the step (B) is wet-etched to form (P) of the step (C).
KR1019930026303A 1993-12-03 1993-12-03 Method of isolation of a semiconductor device KR960014447B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930026303A KR960014447B1 (en) 1993-12-03 1993-12-03 Method of isolation of a semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930026303A KR960014447B1 (en) 1993-12-03 1993-12-03 Method of isolation of a semiconductor device

Publications (2)

Publication Number Publication Date
KR950021349A KR950021349A (en) 1995-07-26
KR960014447B1 true KR960014447B1 (en) 1996-10-15

Family

ID=19369760

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019930026303A KR960014447B1 (en) 1993-12-03 1993-12-03 Method of isolation of a semiconductor device

Country Status (1)

Country Link
KR (1) KR960014447B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100729017B1 (en) * 2006-01-05 2007-06-14 주식회사 케이이씨 Isolation structure method of making of of semiconductor device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100487412B1 (en) * 2002-09-24 2005-05-03 매그나칩 반도체 유한회사 Method for fabricating of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100729017B1 (en) * 2006-01-05 2007-06-14 주식회사 케이이씨 Isolation structure method of making of of semiconductor device

Also Published As

Publication number Publication date
KR950021349A (en) 1995-07-26

Similar Documents

Publication Publication Date Title
KR0169275B1 (en) Semiconductor device having trench structure for element isolating regions and fabricating method therefor
US4729006A (en) Sidewall spacers for CMOS circuit stress relief/isolation and method for making
US4519128A (en) Method of making a trench isolated device
US5166767A (en) Sidewall contact bipolar transistor with controlled lateral spread of selectively grown epitaxial layer
JPH04250650A (en) Flattening of integrated circuit provided with completely recessed isolation insulator
US4887144A (en) Topside substrate contact in a trenched semiconductor structure and method of fabrication
JP2929419B2 (en) Method for manufacturing semiconductor device
US6143623A (en) Method of forming a trench isolation for semiconductor device with lateral projections above substrate
TWI759878B (en) Semiconductor device and manufacturing method thereof
US5742088A (en) Process having high tolerance to buried contact mask misalignment by using a PSG spacer
KR0157875B1 (en) Manufacture of semiconductor device
KR930011500B1 (en) Isolation method of semiconductor
KR960014447B1 (en) Method of isolation of a semiconductor device
US5851901A (en) Method of manufacturing an isolation region of a semiconductor device with advanced planarization
US6100140A (en) Manufacturing method of semiconductor device
EP0146760B1 (en) One mask technique for substrate contacting in integrated circuits
US5763316A (en) Substrate isolation process to minimize junction leakage
KR100839894B1 (en) Semiconductor device and fabrication method therefor
JPS6252950B2 (en)
KR100209280B1 (en) Method for forming a contact of semiconductor device
KR100195227B1 (en) Isolation method in semiconductor device
KR0161191B1 (en) Fabricating method of semiconductor device
KR19990056756A (en) Manufacturing Method of Analog Semiconductor Device
KR0171978B1 (en) Method of manufacturing semiconductor device
JPH0335528A (en) Manufacture of semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
N231 Notification of change of applicant
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
LAPS Lapse due to unpaid annual fee