JPH01132221A - Da converting circuit - Google Patents

Da converting circuit

Info

Publication number
JPH01132221A
JPH01132221A JP29092887A JP29092887A JPH01132221A JP H01132221 A JPH01132221 A JP H01132221A JP 29092887 A JP29092887 A JP 29092887A JP 29092887 A JP29092887 A JP 29092887A JP H01132221 A JPH01132221 A JP H01132221A
Authority
JP
Japan
Prior art keywords
digital signal
circuit
bits
converting
conversion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP29092887A
Other languages
Japanese (ja)
Inventor
Kazuhisa Ishiguro
和久 石黒
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP29092887A priority Critical patent/JPH01132221A/en
Publication of JPH01132221A publication Critical patent/JPH01132221A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To widely shorten a convertion time by separating an input digital signal into a high-order bit and a low-order bit, DA-converting one of them by a resistive dividing type converting part, DA-converting the other by an integration type converting part, adding the outputs of the two converting parts and obtaining an output analog signal. CONSTITUTION:A first converting part 21 is the resistive dividing type converting part composed of resistors 22-25 connected in series between a power source +Vr1 and an earth and switches 26-29 whose one ends are connected with the connection midpoints of the resistors 22-25. When the input digital signal is 4-bit, the digital signal of high-order 2 bits is selected by a first selecting circuit 17, latched by a latch circuit 19 and impressed on a decoder 20. The digital signal of low-order 2 bits is selected by a second selecting circuit 18 and latched by a latch circuit 2 of an integration type second converting part 30. The decoder 20 decodes the digital signal of the high-order 2 bits and generates a control signal to open-close-control the switches 26-29. An adding circuit 31 adds the outputs of the two converting parts. A converting speed is determined by integration time to the digital signal of the low-order bits and it is widely shortened comparing with a conventional case.

Description

【発明の詳細な説明】 (り産業上の利用分野 本発明は、デジタル信号をアナログ信号に変換する為の
DA変換回路に関するもので、特に変換速度音大幅に短
縮し得るDA変換回路に関する。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a DA conversion circuit for converting a digital signal to an analog signal, and more particularly to a DA conversion circuit that can significantly reduce conversion speed.

(ロ)従来の技術 昭和58年9月25日付でオーム社より発行された「A
/Dコンバータ入門」第162頁及び第163頁には、
積分型のDA変換回路が提示きれている。
(b) Conventional technology A published by Ohmsha on September 25, 1980
/D Converter Introduction” pages 162 and 163,
An integral type DA conversion circuit has been presented.

前記積分型のDA変換回路は、直線性、単調性に優れて
いる為にデジタルオーディオ分野等で現在利用されてい
る。第2図は、その様な積分型のDA変換回路を示すも
ので、入力端子(1)に印加される入力デジタル信号は
、ラッチ回路(2)でラッチされデジタル比較回路(3
)に印加される。
The above-mentioned integral type DA conversion circuit is currently used in the field of digital audio and the like because it has excellent linearity and monotonicity. Figure 2 shows such an integral type DA converter circuit, in which the input digital signal applied to the input terminal (1) is latched by the latch circuit (2) and sent to the digital comparator circuit (3).
) is applied to

また、前記デジタル比較回路(3)には、カウンタ(4
)の計数出力が印加されており、前記カウンタ(4)は
制御回路(5)によりその計数動作が制御される様に成
されている。デジタル信号をアナログ信号に変換する変
換部は、増幅回路(6)、第1及び第2スイツチ(7)
及び(8)、コンデンサ(9)及び抵抗(lO)から成
る積分回路(11)と、該積分回路(11)の出力信号
をサンプルホールドするサンプルホールド回路(12〉
とによって構成されており、前記制御回路(5)から発
生する制御信号により前記第1及び第2スイツチ(7)
及び(8)を開閉制御することにより、積分動作が行な
われる。
The digital comparison circuit (3) also includes a counter (4).
) is applied to the counter (4), and the counting operation of the counter (4) is controlled by a control circuit (5). The conversion unit that converts a digital signal into an analog signal includes an amplifier circuit (6), first and second switches (7)
and (8), an integrating circuit (11) consisting of a capacitor (9) and a resistor (lO), and a sample hold circuit (12) that samples and holds the output signal of the integrating circuit (11).
The first and second switches (7) are controlled by a control signal generated from the control circuit (5).
Integral operation is performed by controlling the opening and closing of (8) and (8).

第2図のDA変換回路を用いてDA変換を行なう場合、
まず制御回路(5)から第1制御信号Slを発生させ、
第1スイツチ(7)を閉にし、コンデンサ(10)を放
電させる。その後、前記第1制御信号S1を停止させる
とともに前記制御回路(5)から第2制御信号S、を発
生させ、第2スイツチ(8)を閉にし、積分動作を開始
させる。同時に、カウンタ(4)の計数動作を開始させ
る。前記カウンタ(4)の計数動作は、ラッチ回路(2
〉の出力信号の値とカウンタ(4)の計数値とが一致し
、デジタル比較回路(3)から一致信号が発生する進行
なわれる。前記一致信号が発生すると、制御回路(5〉
からの第2制御信号S、が停止し、第2スイツチク8)
が開となり、積分動作が停止する。積分回路(11)の
出力信号は、その後サンプルホールド回路(12)でサ
ンプルホールドされ、出力端子(13)に入力デジタル
信号に対応した出力アナログ信号が発生する。
When performing DA conversion using the DA conversion circuit shown in Fig. 2,
First, a first control signal Sl is generated from the control circuit (5),
Close the first switch (7) and discharge the capacitor (10). Thereafter, the first control signal S1 is stopped and the second control signal S is generated from the control circuit (5), the second switch (8) is closed, and the integration operation is started. At the same time, the counting operation of the counter (4) is started. The counting operation of the counter (4) is performed by a latch circuit (2).
The value of the output signal of > matches the count value of the counter (4), and a match signal is generated from the digital comparator circuit (3). When the coincidence signal is generated, the control circuit (5)
The second control signal S, from the second switch 8) is stopped.
is opened and the integral operation stops. The output signal of the integrating circuit (11) is then sampled and held in a sample and hold circuit (12), and an output analog signal corresponding to the input digital signal is generated at the output terminal (13).

基準端子(14)に印加される基準電圧を−Vrとずれ
ば、抵抗(9)に流れる電流■は、 〔ただし、Rは抵抗(9)の抵抗値〕 となる。また、コンデンサ(10)は、前記抵抗(9)
に流れる電流工により定1「流充電される為、前記コン
デンサ(10〉の両端電圧Vcは、■ Vc=−t          ・・・・・・・・・・
・・・・・(2)となる。その場合、クロック端子(1
5)に印加されるクロック信号の周期をT1一致信号が
発生する迄のカウンタ(4)の計数値をnとすれば、と
なり、前記第(1)及び(3)式より、となる。従って
、第2図のDA変換回路を用いれば、入力デジタル信号
(前記nが対応)をアナログ信号(前記vcが対応)に
変換することが出来、このアナログ信号をサンプルホー
ルドすれば、出力端子(13)に出力アナログ信号を得
ることが出来る。
If the reference voltage applied to the reference terminal (14) is shifted from -Vr, the current (2) flowing through the resistor (9) will be as follows: [where R is the resistance value of the resistor (9)]. Further, the capacitor (10) is connected to the resistor (9).
Since the current flowing through the capacitor (10) is charged with a constant current of 1, the voltage Vc across the capacitor (10) is: ■ Vc=-t ・・・・・・・・・・・・
...(2). In that case, the clock terminal (1
5) If the count value of the counter (4) until the T1 coincidence signal is generated is n, then from the above equations (1) and (3), the following equation is obtained. Therefore, by using the DA conversion circuit shown in Fig. 2, it is possible to convert the input digital signal (corresponding to n above) into an analog signal (corresponding to vc above), and if this analog signal is sampled and held, the output terminal ( 13) An output analog signal can be obtained.

(ハ)発明が解決しようとする問題点 しかしながら、第2図の如き積分型のDA変換回路は、
積分時間が入力デジタル信号のビット数に対応して増加
する為、高次ビットになるほど計数すべきクロック数の
最大値(HMA! )が増大し、変換時間が非常に長く
なるという問題がある。例えば、Nビットの変換を行な
う場合、前記nM□は2N−1となり、N=8とすれば
nMAx= 255となり、N=16とすればnvAx
= 65535となるので、高次ビットのDA変換回路
としては、現実に使用出来ない。
(c) Problems to be solved by the invention However, the integral type DA conversion circuit as shown in FIG.
Since the integration time increases in accordance with the number of bits of the input digital signal, there is a problem that the maximum value (HMA!) of the number of clocks to be counted increases as the bits become higher, and the conversion time becomes extremely long. For example, when performing N-bit conversion, the nM□ becomes 2N-1, if N = 8, nMAx = 255, and if N = 16, nvAx
= 65535, so it cannot actually be used as a high-order bit DA conversion circuit.

(ニ)問題点を解決するための手段 本発明は、上述の点に鑑み成されたもので、入力デジタ
ル信号を上位ビット及び下位ビットに分離する手段と、
分離きれた上位ビット及び下位ビットの一方のデジタル
信号をデコードするデコーダと、直列接続された複数の
抵抗とスイッチとから成り、前記デコーダ出力に応じて
アナログ信号を発生する第1変換部と、分離された上位
ビット及び下位ビットの他方のデジタル信号を積分して
アナログ信号を発生する第2変換部と、前記第1及び第
2変換部の出力アナログ信号を加算する加算回路とを備
える点を特徴とする。
(d) Means for solving the problems The present invention has been made in view of the above points, and includes means for separating an input digital signal into upper bits and lower bits;
a decoder that decodes a digital signal of one of the separated upper bits and lower bits; a first conversion section that includes a plurality of resistors and switches connected in series and generates an analog signal according to the output of the decoder; A second conversion section that integrates the other digital signal of the upper bits and lower bits to generate an analog signal, and an addition circuit that adds the output analog signals of the first and second conversion sections. shall be.

(ネ)作用 本発明に依れば、入力デジタル信号を上位ビット及び下
位ビットに分離し、その一方を抵抗分割型の第1変換部
でDA変換し、その他方を積分型の第2変換部でDA変
換し、両度換部の出力信号を加算して出力アナログ信号
を得る様にしているので、変換時間を大幅に短縮出来る
とともに、高精度のDA変換回路を提供出来る。
(f) Effect According to the present invention, an input digital signal is separated into upper bits and lower bits, one of which is subjected to DA conversion in the first converter of resistance division type, and the other is converted to analogue by the second converter of integral type. Since the output analog signal is obtained by adding the output signals of the two-way converter, the conversion time can be significantly shortened, and a highly accurate DA conversion circuit can be provided.

(へ)実施例 第1図は、本発明の一実施例を示す回路図で、(16)
は入力デジタル信号が印加される入力端子、(17)は
前記デジタル信号の上位ビットを選択する分離手段とし
て動作する第1選択回路、(18)は前記デジタル信号
の下位ビットを選択する分離手段として動作する第2選
択回路、(19)は前記第1選択回路(17)の出力信
号をラッチするラッチ回路、(20)は該ラッチ回路(
19)の出力信号をデコードするデコーダ、(4,)は
電源(+Vr+)とアース間に直列接続された第1乃至
第4抵抗(22)乃至(25)と、一端が前記第1乃至
第4抵抗(22)乃至(25)の接続中点に接続された
第1乃至第4スイツチ(26)乃至(29)とから成る
第1変換部、(廷)は前記第2選択回路(18)の出力
信号をDA変換する積分型の第2変換部、(31)は前
記第1及び第2変換部(麩)及び(隠)の出力信号を加
算する加算回路、及び(32)は出力アナログ信号が得
られる出力端子である。尚、積分型の第2変換部(亜)
はその構成及び動作が第2図のDA変換回路と同一に付
、同一の符号を付し、説明を省略する。
(f) Embodiment FIG. 1 is a circuit diagram showing an embodiment of the present invention, (16)
is an input terminal to which an input digital signal is applied; (17) is a first selection circuit that operates as a separation means for selecting the upper bits of the digital signal; and (18) is a separation means for selecting the lower bits of the digital signal. The operating second selection circuit (19) is a latch circuit that latches the output signal of the first selection circuit (17), and (20) is the latch circuit (20).
A decoder (4,) decodes the output signal of 19), which includes first to fourth resistors (22) to (25) connected in series between the power supply (+Vr+) and the ground, and one end of which is connected to the first to fourth resistors (22) to (25). A first converting section (former) consisting of first to fourth switches (26) to (29) connected to the connection midpoints of resistors (22) to (25) is connected to the second selection circuit (18). (31) is an addition circuit that adds the output signals of the first and second converters (fu) and (hidden); and (32) is an output analog signal. This is the output terminal that provides the output. In addition, the integral type second conversion section (sub)
The structure and operation are the same as those of the DA conversion circuit of FIG. 2, and the same reference numerals are given, and the explanation will be omitted.

いま、入力デジタル信号を4ビツトとすれば、上位2ビ
ツトのデジタル信号が第1選択回路(17)で選択され
、ラッチ回路(19)でラッチされてデコーダ(20)
に印加される。また、下位2ビツトのデジタル信号が第
2選択回路(18)で選択され、第2変換部(廷)のラ
ッチ回路(2)にラッチされる。
Now, if the input digital signal is 4 bits, the upper 2 bits of the digital signal are selected by the first selection circuit (17), latched by the latch circuit (19), and sent to the decoder (20).
is applied to Further, the lower two bits of the digital signal are selected by the second selection circuit (18) and latched by the latch circuit (2) of the second converting section.

前記デコーダ(20)は、上位2ビツトのデジタル信号
をデコードし、第1乃至第4スイツチ(26)乃至(2
9)を開閉制御する為の第1乃至第4制御信号を発生す
る。すなわち2ビツトのデジタル信号「00」、’01
J%  ’10J%  ’11」を4種類の第1乃至第
4制御信号’ o o 01 J、’0010」、’0
100J、rlooo」に変換する。
The decoder (20) decodes the upper 2 bits of the digital signal and decodes the first to fourth switches (26) to (2).
9) Generate first to fourth control signals for controlling opening/closing. In other words, 2-bit digital signals "00", '01
J% '10J% '11' as four types of first to fourth control signals' o o 01 J, '0010', '0
100J, rlooo".

例えば、2ビツトのデジタル信号が110」の場合、第
3制御信号’0100Jが発生し、第2スイツチ(27
)を閉にする。第1乃至第4抵抗(22)乃至(25)
の値を等しく設定すれば、第2スイツチ(27)を介し
て加算回路(31)に印加される電圧■、は、となる。
For example, when the 2-bit digital signal is 110'', the third control signal '0100J is generated and the second switch (27
) to close. First to fourth resistors (22) to (25)
If the values of .

また、積分型の第2変換部(東)の出力電圧V、は、前
記第(4)式に応じて、 Vr。
Further, the output voltage V of the integral type second conversion section (east) is Vr according to the above equation (4).

V、=−・nT       ・・・・・・・・・・・
・・・・・・・(6)CR 〔ただし、−Vrtは基準端子(14)に印加される基
準電圧〕 となる。加算回路(31)は、前記電圧V、及びV、を
加算する。その為、出力端子(32)に発生する出力ア
ナログ電圧v0は1 、。=v、+v、=血+血、n001010066.(
7)   CR となる。前記電源電圧Vr+と前記基準電圧−Vrtと
の関係を適切に設定すれば、出力アナログ電圧V。
V, =-・nT ・・・・・・・・・・・・
(6) CR [However, -Vrt is the reference voltage applied to the reference terminal (14)]. The addition circuit (31) adds the voltages V and V. Therefore, the output analog voltage v0 generated at the output terminal (32) is 1. =v, +v, =blood+blood, n001010066. (
7) Becomes CR. If the relationship between the power supply voltage Vr+ and the reference voltage -Vrt is appropriately set, the output analog voltage V.

は、入力デジタル信号に対応したものとなり、DA変換
が達成される。
corresponds to the input digital signal, and DA conversion is achieved.

第1図のDA変換回路の場合、変換速度は下位ビットの
デジタル信号に対する積分時間により決まり、従来の場
合と比べ大幅に短縮される。例えは、4ビツトのデジタ
ル信号をDA変換する場合、第2図の回路の場合、最大
15(=2N−1)クロック分の時間がかかったが、第
1図の回路の場合は、最大3(=2”−1)クロック分
の時間でDA変換を行なうことが出来る。変換時間の短
縮効果は、入力デジタル信号のビット数が増加するほど
大となり、例えば16ビツトのデジタル信号の場合、最
大65535クロック分の時間がかかっていたのを、2
55クロック分の時間に短縮出来る。
In the case of the DA conversion circuit shown in FIG. 1, the conversion speed is determined by the integration time for the digital signal of the lower bits, and is significantly reduced compared to the conventional case. For example, when converting a 4-bit digital signal from digital to analog, the circuit in Figure 2 takes a maximum of 15 (=2N-1) clocks, but the circuit in Figure 1 requires a maximum of 3 clocks. DA conversion can be performed in a time equivalent to (=2"-1) clocks.The effect of reducing conversion time increases as the number of bits of the input digital signal increases. For example, in the case of a 16-bit digital signal, the maximum It used to take 65,535 clocks, but now it is 2
The time can be reduced to 55 clocks.

尚、第1図の実施例においては、上位ビットのDA変換
を抵抗分割型で、下位ビットのDA変換を積分型で行な
っている為、変換時間の短縮とともに、変換精度を向上
させることが出来る。しかしながら本発明は、それに限
定されるものでは無く、逆に上位ビットを積分型で、下
位ビットを抵抗分割型でDA変換してもよい。
In the embodiment shown in FIG. 1, the DA conversion of the upper bits is performed by a resistor division type, and the DA conversion of the lower bits is performed by an integral type, so that it is possible to shorten the conversion time and improve the conversion accuracy. . However, the present invention is not limited thereto, and conversely, the upper bits may be converted into an integral type, and the lower bits may be converted into a resistor using a resistance division type.

(ト)発明の効果 以上述べた如く、本発明に依れば、変換時間を大幅に短
縮出来るDA変換回路を提供出来る。特にデジタルオー
ディオ分野の如く、多ビットのDA変換回路を必要とす
る場合に、本発明に係るDA変換回路は好適である。
(G) Effects of the Invention As described above, according to the present invention, it is possible to provide a DA conversion circuit that can significantly shorten conversion time. The DA conversion circuit according to the present invention is particularly suitable when a multi-bit DA conversion circuit is required, such as in the field of digital audio.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、本発明の一実施例を示す回路図、及び第2図
は従来のDA変換回路を示す回路図である。 〈16)・・・入力端子、 (17)、 (18)・・
・選択回路(分離手段)、 (20)・・・デコーダ、
 (ハ)・・・第1変換部、 (東)・・・第2変換部
、 (31)・・・加算回路、(32)・・・出力端子
FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing a conventional DA conversion circuit. <16)...Input terminal, (17), (18)...
・Selection circuit (separation means), (20)...decoder,
(c)...first conversion section, (east)...second conversion section, (31)...addition circuit, (32)...output terminal.

Claims (1)

【特許請求の範囲】[Claims] (1)入力デジタル信号を上位ビット及び下位ビットに
分離する手段と、分離された前記上位ビット及び下位ビ
ットの一方のデジタル信号をデコードするデコーダと、
直列接続された複数の抵抗及びそれらの接続点に一端が
接続され、前記デコーダの出力信号により開閉制御され
るスイッチとから成り、前記一方のデジタル信号に応じ
たアナログ電圧を発生する抵抗分割型の第1変換部と、
分離された前記上位ビット及び下位ビットの他方のデジ
タル信号を積分し、対応するアナログ電圧を発生する積
分型の第2変換部と、前記第1及び第2変換部の出力ア
ナログ信号を加算する加算回路とから成るDA変換回路
(1) means for separating an input digital signal into upper bits and lower bits, and a decoder for decoding one of the separated digital signals of the upper bits and lower bits;
A resistor-divided type consisting of a plurality of resistors connected in series and a switch whose one end is connected to the connection point of the resistors and whose opening/closing is controlled by the output signal of the decoder, and which generates an analog voltage according to the one digital signal. a first conversion section;
an integral type second conversion section that integrates the other separated digital signal of the upper bit and the lower bit and generates a corresponding analog voltage; and an addition that adds the output analog signals of the first and second conversion sections. A DA conversion circuit consisting of a circuit.
JP29092887A 1987-11-18 1987-11-18 Da converting circuit Pending JPH01132221A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP29092887A JPH01132221A (en) 1987-11-18 1987-11-18 Da converting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP29092887A JPH01132221A (en) 1987-11-18 1987-11-18 Da converting circuit

Publications (1)

Publication Number Publication Date
JPH01132221A true JPH01132221A (en) 1989-05-24

Family

ID=17762323

Family Applications (1)

Application Number Title Priority Date Filing Date
JP29092887A Pending JPH01132221A (en) 1987-11-18 1987-11-18 Da converting circuit

Country Status (1)

Country Link
JP (1) JPH01132221A (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5181551A (en) * 1975-01-16 1976-07-16 Hitachi Ltd FUKUGOKI
JPS5610738A (en) * 1979-07-09 1981-02-03 Yokogawa Hokushin Electric Corp Digital-to-analog converter
JPS59163912A (en) * 1983-03-08 1984-09-17 Toshiba Corp C-r type da converter
JPS59201519A (en) * 1983-04-28 1984-11-15 Sanyo Electric Co Ltd Digital-analog converter
JPS60100831A (en) * 1983-11-07 1985-06-04 Sony Corp Digital/analog converter

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5181551A (en) * 1975-01-16 1976-07-16 Hitachi Ltd FUKUGOKI
JPS5610738A (en) * 1979-07-09 1981-02-03 Yokogawa Hokushin Electric Corp Digital-to-analog converter
JPS59163912A (en) * 1983-03-08 1984-09-17 Toshiba Corp C-r type da converter
JPS59201519A (en) * 1983-04-28 1984-11-15 Sanyo Electric Co Ltd Digital-analog converter
JPS60100831A (en) * 1983-11-07 1985-06-04 Sony Corp Digital/analog converter

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