JPH03248623A - Successive comparison type a/d converter - Google Patents

Abstract

PURPOSE:To halve the number of circuit components of a counter in comparison with those of a conventional converter by inverting or noninverting a digital value supplied from the counter in response to the result of comparison between an input analog voltage and an initial A/D conversion output. CONSTITUTION:The MSB of a counter 11 is set to logical '1' by converting the level of a reset terminal 13 to an H level and other bits are reset to '0'. An R-SFF 16 is set through a NOR gate 22, and AND gate 17A of a multiplexer 14A is opened, the count of a counter 11 is inputted as it is to a D/A converter 19, from which a D/A conversion output VDA. After the level of a terminal 13 is set to an L level, a clock phi1 rises to an H level and a level VCO is latched by a latch circuit. An FF 16 is reset by changing the output of the gate 22 to an L level, and since a terminal Q goes to an L level and a terminal, inverse of Q goes to an H level, an AND gate 17B of multiplexers 14A-14D is opened. The output of an inverter 25 is at an H level, an AND gate 26 is opened and a counter 11 starts count-up.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Industrial Application Field The present invention relates to a successive approximation type A/D converter, and more specifically, to an up/down converter that performs up/down operations of a counter according to comparison results. The present invention relates to a successive approximation type A/D converter that is faster and more accurate by providing a control circuit.

(b) Prior Art FIG. 5 is a circuit diagram showing a successive approximation type A/D converter according to a conventional example.

In the figure, such an A/D converter converts an input analog voltage of 1 A applied to an input terminal (1) and a digital value supplied from a counter (2) into a D/A converter (3).
By successively comparing the converted analog voltage, A/
It performs D conversion.

Next, an example of the operation of such an A/D converter will be explained with reference to FIG.

First, at time t, the counter (2) is switched to the Re5et terminal (4
) is reset to 0 by applying “θ” to D
/A converter output ■ becomes 0■.

The counter (2) counts the clock signal ≠ from the AND gate (5) and outputs V from the D/A converter. A is changed stepwise by step voltage ΔV as shown in the figure.

Thus, when voA becomes greater than the input analog voltage vIA, the output of the comparator is inverted and the AND gate (5)
Close.

The digital output of the counter (2) at this time becomes a digital value corresponding to the input analog voltage.

However, for a full-scale input analog voltage, the counter must count from "0" until all outputs become "1", and in order to improve conversion accuracy, reducing the step voltage ΔV increases the conversion time. There was a drawback.

The prior art regarding this point is disclosed, for example, in Document 1 Latest D/A, A/D Humberta User Manual published by the Japan Center for Technology and Economic Affairs.
2) is replaced with an up/down counter, and a comparator compares the input analog voltage ■ with the D/A converter output, which has been initialized to a level that is half of the full scale, and depending on the comparison result, count up the counter,
There is a technique to reduce conversion time by controlling the countdown.

(c) Problems to be Solved by the Invention Incidentally, an up-down counter has a disadvantage in that it has a larger number of circuit elements than a unidirectional counter, and that it is difficult to increase the speed of the counter.

The present invention was created in view of such conventional problems, and an object of the present invention is to provide a high-speed successive approximation type A/D converter that has a small number of circuit elements and is suitable for high integration.

(d) Means for Solving the Problems The present invention provides a successive approximation type A/D converter including a unidirectional binary counter, in which only the most significant bit of the digital value of the counter is set to "1".
and resets all other bits to "0", the analog voltage completely converted from the initially set digital value and the input analog voltage are compared by a comparator, and the comparison The present invention is characterized in that an up/down control circuit is provided which performs up/down operations of the counter by inverting or non-inverting the digital value supplied from the counter depending on the result.

(*) Effect According to the present invention, the D/A converter output, which is initially set to half the full scale by the initial setting means, and the input analog voltage are compared by the comparator, and the up/down control circuit The input analog voltage is applied to D/
If it is larger than the A converter output, the counter output is output as is to perform a count up,
The D/A converter output is increased in a stepwise manner, and conversely, when the analog voltage is smaller than the D/A converter output, the counter output is inverted and output to perform a countdown. The transducer output can be stepped down.

Therefore, the A/D conversion time can be shortened compared to conventional methods, and the number of circuit elements in the counter can be reduced to about half compared to when an up/down counter is used, contributing to higher integration and higher speed. I can do it.

(F) Embodiment FIG. 1 is a circuit diagram showing a successive approximation type A/D converter according to an embodiment of the present invention.

In the figure, (11) is a 4-bit unidirectional counter, and four flip-flops (12A) to (12
D) is connected so that the output Q is input to the trigger input T of the next stage.

(13) is a reset terminal for initializing the counter (11), and the most significant bit (hereinafter referred to as MSB)
Flip-flops (12D) (7) set corresponding to S and other flip-flops (12A) to (12C)
This is the first feature of the present invention.

(14A) is the output Q of the flip-flop (12A)
and an inverted output inverted by an inverter (15) according to the values of the outputs Q and Q of the R-S flip-flop (16). and NOR gate (1
8), which is the second feature of the present invention. (14B) to (14D) are multiplexers having the same configuration.

(19) is a D/A converter for converting the digital outputs of the multiplexers (14A) to (14D) into analog values corresponding to the values thereof, and is a D/A converter that converts the digital outputs of the multiplexers (14A) to (14D) into analog values corresponding to the reference voltage (AV''-AV
-) into (2'-1) pieces and a decoder circuit.

20) is the analog input voltage VIA and the D/A conversion output V. This is a comparator that compares A.

(21) is a latch circuit that latches the output V co of the comparator (20), and the clock signal -1 has been inputted.

(22) is a NOR gate, and latch circuit (21)
The output and Reset signal are input, and the NOR gate (2
The output of 2) and the output inverted by the inverter (23) are connected to the set power S and reset power R of the R-S blip prop (16), respectively.

(24) is a so-called exclusive OR circuit, and the comparator (
20) Output V. 0 and the latch circuit (21) output are input.

(25) is an inverter that inverts the output of the exclusive OR circuit (24).

(26) is an AND gate, and is an inverter 25)
An output and a clock pulse φ for driving the counter are input.

The output Start of the AND gate (26) is the counter (
11) is connected to the trigger input of a flip-flop (12A) corresponding to the least significant bit (hereinafter referred to as LSB).

Next, an example of the operation of such a successive approximation type A/D converter will be explained with reference to FIG.

First, by changing the Reset terminal (13) from a low level (hereinafter referred to as L level) to a high level (hereinafter referred to as H level), the MSB of the counter (11) is set to "
1” and reset the other bits to “0”.

That is, the value of the counter is initially set to "1000".

In this case, the R-S flip-prop is a NOR gate (2
2), Q is set to H level and Q is set to L level, so A of multiplexers (14A) to (14D)
The ND gate (17A) side is opened, and the value of the counter is directly input to the D/A converter (19), resulting in a D/A conversion output. Ai (initialized ■..

Outputs (AV"-AV-)) to =.

Here, VIA<V. In the case of Ai, the comparator output VCO becomes L level.

Next, after setting the Reset terminal to L level, the clock -
1 to H level, VCO is latched circuit (21)
Latch with.

When the output of the NOR gate (22) changes to L level, the R-S flip-flop (16) is reset, and Q becomes L level and Q becomes H level, so the AND of multiplexers (14A) to (14D) is performed. Gate (17B
) side opens.

In this case, the output of the latch circuit (21) and the comparator output are both at L level, so the exclusive OR circuit (24)
The output of the inverter (25) through is at H level,
AND game 26) opens and the counter (11) starts counting up.

By the way, since the multiplexers (14A) to (14D) have inverted outputs selected, each bit of the initially set value "1000" of the counter (11) is inverted and the output of the multiplexers (14A) to (14D) is selected. 011 at the output stage
1”.

Next, the counted up value "1001" is inverted to "0110", and the countdown continues in the same manner.

Thus, the output V of the D/A converter (19). A falls stepwise as shown in FIG. 3, and when vIA>vOA, y co changes to H level. in this case,
Since the output of the latch circuit (21) maintains the L level, the output of the inverter (2
The output of 5) changes to L level, and the AND gate (26)
is closed to stop the operation of the counter (11).

At this time, the values of multiplexers (14A) to (14D) (
For example, "0011") is the digital value corresponding to the input analog voltage VIA.

Then, if VIA>VoAi('), the comparator output VC
O becomes H level and R-S flip-flop (16)
is set, multiplexers (14A) to (140)
The AND gate (17A) side of is opened.

Therefore, in this case, the value of the counter (11) is counted up without being inverted and is input to the D/A converter (19).

Thus, the output V of the D/A converter (19). A rises in a stepwise manner as shown in Figure 4, and VIA<■. , the VCO changes to L level.

In this case, since the output of the latch circuit (21) is held at H level, the output of the inverter (25) through the exclusive OR circuit (24) changes to L level, closing the AND gate (26). to stop the operation of the counter (11).

The values of the multiplexers (14A) to (14D) at this time become digital values corresponding to the input analog voltage VIA.

According to the above, the present invention is based on V. Ai is initially set to a level at full scale, V, A<V. In case of Ai, V. A descends in a stepwise manner, and if VIA>VOAi, ■. , can be changed to rise in a stepwise manner, so A/D
Conversion time can be shortened. Moreover, the number of circuit elements in the counter can be reduced to about half compared to the case where an up-down counter is used, contributing to higher integration and higher speed.

Although this embodiment has been described with reference to the case where the unidirectional counter is an up counter, it goes without saying that it can also be applied when the unidirectional counter is a down counter.

(G) As described in detail, the present invention includes an initial setting means for setting only the most significant bit of the digital value of the counter to "1" and resetting all other bits to "0". , an up/down control circuit is provided that performs up/down operations of the counter by inverting or non-inverting the digital value supplied from the counter according to the comparison result between the input analog voltage and the initial A/D conversion output. Therefore, the conversion time can be reduced compared to a conventional successive approximation type A/D converter using a unidirectional counter.

Furthermore, compared to conventional successive approximation type A/D converters that use up/down counters, the circuit elements of the counter can be reduced to about half, resulting in highly integrated and faster successive approximation type A/D converters. can be provided.

[Brief explanation of drawings]

1 is a circuit diagram showing a successive approximation type A/D converter according to an embodiment of the present invention; FIG. 2 is a timing chart of an operation example of the successive approximation type A/D converter shown in FIG. 1; 3 and 4 are diagrams showing the operation of the successive approximation type A/D converter shown in FIG. 1. FIG. 5 is a circuit diagram showing a successive approximation type A/D converter according to a conventional example, and FIG. 6 is a diagram showing the operation of the successive approximation type A/D converter shown in FIG.

Claims (1)

[Claims] (1) Successive approximation type A that converts the digital value supplied from a unidirectional binary counter into an analog voltage, and compares the analog voltage with the input analog voltage using a comparator.
In the /D converter, initial setting means is provided for setting only the most significant bit of the digital value to "1" and resetting all other bits to "0" in the initial state of the counter, and the initial setting A comparator compares the analog voltage converted from the digital value and the input analog voltage, and inverts or non-inverts the digital value supplied from the counter depending on the result of the comparison, thereby increasing the counter.・Successive approximation type A/D characterized by being equipped with an up/down control circuit that performs down operation
converter.