JPH01129453A - Semiconductor device - Google Patents

Abstract

PURPOSE:To utilize space effectively, and to simplify the arrangement of fundamental gates for a Bi-CMOS by keeping the length of a rectangular region in the longitudinal direction constant regardless of the kinds of the fundamental gates, arraying adjacent fundamental gates in the cross direction, and dividing the forming regions of three kinds of transistors into three in the longitudinal direction so that the length in the longitudinal direction of each of the forming regions is held constant. CONSTITUTION:In the forming region BiP of a bipolar transistor, an emitter region is divided into split emitter regions E and a base region into split base regions B, and the regions E and B are disposed alternately in the cross direction, and connected mutually in parallel. In a MOS type transistor region, a source region S, a gate region G and a drain region D are partitioned respectively into a plurality of regions, and arrayed repeatedly in the cross direction regularly in fixed order. Since the same element regions are adjoined in the cross direction, even gates of different kinds can be arranged without considering approach rules among elements, length Lv in one longitudinal direction is not considered in length Lv in the longitudinal direction of fundamental gates, and the gates can be disposed according to a pattern considering only length in the cross direction.

Description

[Detailed description of the invention] [Summary] Bipolar transistor and 0MOS (Complc-m
entry Metal Oxide Sem1
With regard to semiconductor devices in which transistors and transistors are arranged on the same substrate, for the purpose of effective space utilization and simplification of basic gate arrangement, bipolar transistors, N-channel MOS transistors, and P-channel MO3 transistors are arranged on the same substrate. In a semiconductor device formed in a rectangular area on a substrate, basic gates adjacent to the rectangular area in the horizontal direction are arranged with the vertical length of the rectangular area constant regardless of the type of basic gate, and The formation region of the three types of transistors is divided into three in the vertical direction, and the length of the formation region of the same type of transistor among the three types of 1-transistor formation regions is constant in the vertical direction, and It is configured to be arranged so as to be lined up in the horizontal direction.

[Industrial application field]

The present invention relates to a semiconductor device, and particularly to a semiconductor device in which a bipolar transistor and an 0MOS transistor are arranged on the same board. Regarding i-placement.

B+-cMo whose logic is configured with CMOSI transistors and the load is driven with bipolar transistors.
sg This gate is a bipolar transistor CMOSt
- Since it has a higher driving capacity than a transistor, it can charge a load faster than a 0M08 circuit, and since a steady current does not flow like an ECL circuit, it has the advantage of lower power consumption than an ECL circuit.

This is how the i-CMOS basic gate is a NOT circuit (
(inverter), NAND circuit, and NOR circuit, and must be arranged by effectively utilizing the limited space on the semiconductor substrate.

[Conventional technology]

Figure 5 shows the circuit diagram of B i-0M081 gate,
3(A) shows an NOV circuit (inverter), FIG. 2(B) shows a two-man powered NAND circuit, and FIG. 4(C) shows a two-man powered NOR circuit.

The inverter shown in FIG. 5 (A>) is a CMOS inverter consisting of a P-channel MOS transistor Q1 and an N-channel MOS transistor Q2.
The input terminal (the connection point between the gates of Ql and Ql) is connected to the gate of the N-channel MOS transistor Q3, and the input terminal (the connection point of each gate of Ql and Ql) is connected to the gate of the
4 and an NPNt-transistor Q6 are connected as shown in the figure, and an output signal having the opposite logic value to the input signal is obtained from the connection point between the emitter of the transistor Q5 and the collector of the transistor Q6.

Furthermore, the two-man power NAND circuit shown in FIG. 5(B) consists of P-channel MOS transistors Qy and Qa, N-channel MOS transistors 09 to Q13, and NPN transistors Q+4 and Qls, and the two-man power is only at a high level. Transistors Q7 and Qa are turned off, transistor Q14 is turned off, and transistor Q
+s is turned on to obtain a low level output signal, and when at least one of the two inputs is at a low level, one of Ql and Qa is turned on, turning on transistor Q14, and turning off transistor Q+s, Obtain a high level output signal.

Furthermore, the two-man power NOR circuit shown in FIG.
- Consisting of transistors Q23 and Q24, transistors QI6 and Q only when both are at low level.
ly are respectively turned on and the transistor Q, ! 3 is turned on, transistors QI9 and Q2+ are turned off, and transistor Q24 is turned off to obtain a high level output ffl =. When at least one of the two inputs is at a high level, one of QCs and Q17 is turned on. A low level output signal is obtained by turning off the transistor Q23 and turning on at least one of Q10 and Q21 to turn on the transistor Q23.

The transistor size of the B i-0M08 single gate with this configuration is determined to be optimal for the standard mouth volume, and when the load capacity is W compared to the standard one (Y, all 1~ The transistor size was changed accordingly.

[The problem that the invention attempts to solve]

As shown in Figures 5(A) to (C), 3i-CMO
The types of S basic gates are (inverter.

Since the number of transistors differs depending on the type (NAND, N0R), the physical dimensions differ depending on the type, and even the same type of Bi-CMO3W main gate has different physical dimensions depending on the load capacity Φ.

On the other hand, when basic gates are actually developed on a semiconductor substrate, the approach rule between two adjacent wooden gates is determined by the approach rule between elements (the approach rule between wells). If they are different, the arrangement of elements inside the M gates will also be different, so it cannot be determined uniformly.

Conventionally, when placing a basic gate on a semiconductor V-board,
Since the basic gates were placed in an appropriate space, there was a problem in that it required a considerable amount of effort to effectively utilize the space and place the basic gates.

The present invention has been made in view of the above points, and it is an object of the present invention to provide a semiconductor device that can realize effective use of space and simplification of the gate arrangement of the Br-cMosm.

[Means for solving problems]

FIG. 1 shows the original configuration of the present invention. In the figure, 1a.

lb and 1c are rectangular areas constituting basic gates, Bi
P is the formation region of the bipolar transistor, NMOS
i, t A region where an N-channel MOS transistor is formed, PMO3 is a region where a P-channel MOS transistor is formed.

Further, Lv is the length in the vertical direction of the rectangular regions 1a, ib, and lc, which are constant regardless of the type of basic gate, and the formation region B i P of each transistor.

NMOS,' PMOS (7) Vertical direction (7) ffl;!
Ls, LN.

LP is also made to have the same length between transistor formation regions of the same type.

In addition, rectangular areas 1a, 1b, 1c, Sunawa et al. B i-C
The MO3 basic gates are arranged laterally, forming three types of transistor formation regions BiP and NM.

Forming regions for transistors of the same type among S and PMOS are also arranged horizontally.

[Effect]

Basic gates consisting of a bipolar transistor, an N-channel MOS transistor, and a P-channel MOS transistor are placed on a semiconductor substrate in rectangular regions 1a, lb, and lc.
In a semiconductor device formed in a semiconductor device, the basic gates have a constant length Lv in the vertical direction and are arranged in the horizontal direction, and the same element regions are adjacent to each other, so even if the adjacent basic gates are of different types, there is no difference between the elements. Approach rules (proximity rules between wells) can be arranged without changing π. It is assumed that each element is located at least 1/2 of the proximity rule inside the boundary line of the basic gate.

Further, when power is supplied through second-layer wiring, the wiring can be horizontally arranged in parallel at the same height.

In the present invention, since the length Lv of the basic gate in the vertical direction is constant, it is possible to arrange a pattern by considering only the length in the horizontal direction without considering the length Lv in the vertical direction.

〔Example〕

FIG. 2 shows a layout diagram of an embodiment of a bipolar transistor according to the present invention. This pattern arrangement is shown in Figure 1.
This is carried out within the bipolar transistor formation region indicated by P, where the emitter region is divided into a plurality of divided emitter regions E, and the base region is also divided into a plurality of divided emitter regions E. At the same time as being divided into B, the division Emitsuta is destroyed E
and divided base regions B are arranged alternately in the horizontal direction, and the divided base regions E are connected in parallel with each other, and the divided base regions B are also connected in parallel with each other.

On the other hand, as shown by C, the collector region is formed without being divided.

FIG. 3 shows a layout diagram of an embodiment of a MOS type transistor according to the present invention. In the figure, S is a source region, G is a gate region, and D is a drain region, each of which is divided into a plurality of regions, and each divided region S, G, and D are arranged horizontally in a regular order. are arranged repeatedly.

The pattern arrangement shown in FIG. 3 is performed within the formation region of the MOS type transistor shown as NMOS or PMOS in FIG. Similar items are connected in parallel.

Not shown in Figures 2 and 3, each area is divided and the divided areas of the same scale are connected to each other because in the present invention, the large basic gate is elongated in the horizontal direction. However, if it is too long and thin, it is not desirable in terms of characteristics, so by connecting the divided regions in parallel as described above, a large-sized transistor is formed.

Therefore, with this method, the length Lv of the basic gate in the vertical direction does not need to be changed even when changing the size of the basic gate, and the pattern arrangement δ can be easily created.

Next, embodiments of the present invention according to load ranges will be described with reference to FIG. 4. The physical dimensions of the B i -CMOS basic gate vary depending on the load capacitance, as described above.

Fig. 4 (A) shows the pattern layout of one example of the inverter for the standard load capacity, and Fig. 4 (B) shows the pattern arrangement of one example of the inverter for the standard load capacity.
Figure (C) shows the pattern layout of an embodiment of the inverter for a load capacity R of 5 times that of the standard load capacity. (D) shows a longitudinal sectional view taken along the broken line I in FIG. 5(A), and the same components as in FIG. 5(A) are given the same reference numerals.

+b In the same figure (D), 3 is the P holy substrate, n is the n+ buried layer, p + l) is the P+ buried layer, C is the collector, E is the emitter, B is the base, and the shaded areas are Field oxide is shown. Roughly speaking, 4 is a gate oxide film, 5 is a gate electrode, 6 is a P well, and 7 is an N well.

As can be seen from Fig. 4 (A) to (C), when the load capacity j is the standard size (Fig. 4 (A)), the divided emitter area is 1 it.
! The number of E is four, the number of divided gate regions G is six,
In the same figure (B), which is 1.5 times the size, the number of divided emitter regions E is six, the number of divided gate regions G is nine,
Furthermore, when the size is twice as large (FIG. 6(C)), the number of divided emitter regions E is eight, and the number of divided gate regions G is twelve.

In other words, the above division I mtii! The ratio between the number of E and the number of divided gate regions G is always constant, and the number of divided emitter regions E and divided gate regions G is increased in proportion to the load capacity. Note that each divided area E. B. The individual sizes of G themselves are constant.

In this way, the 3i-CMO is optimal for each of the three types of load situations.
By preparing the S basic gate, most of the practical negative connotations can be dealt with. Note that in order to change the size by 0.5 times, the standard size divided area E. It is sufficient if the number of G's is an even number.

〔Effect of the invention〕

As described above, according to the present invention, the basic gate size to be used can be determined by estimating the load capacity, and thereby the physical dimensions of the basic gate can be accurately determined, and since the length in the vertical direction is constant, Estimating the space when laying out basic gates and arranging basic gates is much easier than before, and since the positions of input lines, output lines, and power supply wiring are unified, wiring is extremely easy to do. It has the following characteristics.

[Brief explanation of the drawing]

Fig. 1 is a configuration diagram of an original drum according to the present invention, Fig. 2 is a layout diagram of an embodiment of a bipolar transistor, Fig. 3 is a layout diagram of an embodiment of a MOS transistor, and Fig. 4 is a diagram showing each implementation of the invention. FIG. 5 is a circuit diagram of a B i -CMO3 basic gate. In the figure, 1a, 1b, 1c are rectangular regions, BiP is a bipolar transistor formation region, NMOS is an N-channel MO3 type transistor formation region, PMO3 is a P-channel MOS transistor formation region, and L is the vertical direction of the rectangular region. The lengths of LB, LN, and LP are 1 to the length in the vertical direction of the transistor forming region. Patent applicant Fujitsu Ltd. Fujitsu VLSI Ltd. 1f)
Figure 7 for bacteria Figure 2 MOS type - Volume 3 - The love of Zista

Claims (3)

[Claims] (1) Basic gates consisting of bipolar transistors, N-channel MOS transistors, and P-channel MOS transistors are connected to rectangular areas (1a, 1b) on the semiconductor substrate.
, 1c), the vertical length (L) of the rectangular region (1a, 1b, 1c) is
v) is constant regardless of the type of basic gate, and the basic gates adjacent in the horizontal direction of the rectangular area (1a, 1b, 1c) are arranged;
Types of transistor formation regions (BiP, NMOS, P
MOS) is divided into three in the vertical direction, and the formation regions of the three types of transistors (BiP, NMOS, PMOS) are divided into three parts in the vertical direction.
), in which transistor formation regions of the same type are arranged to have constant lengths (L_B, L_N, L_P) in the vertical direction and to be aligned in the horizontal direction. (2) Formation region of the bipolar transistor (BiP
), the emitter regions and base regions are each divided and arranged alternately in the horizontal direction, and the plurality of divided emitter regions are connected in parallel, and the plurality of divided base regions are connected in parallel. and the N channels M
Each formation region (NMOS, PMOS) of an OS type transistor and a P channel MOS type transistor has a gate,
Claim 1 characterized in that each of the drain and source regions is divided into a plurality of regions and arranged alternately in the horizontal direction, and the divided regions of the same type are connected in parallel. 1. Semiconductor device described in Section 1. (3) Formation regions of the three types of transistors (BiP,
Among the plurality of divided regions in NMOS, PMOS), the ratio of the number of emitter divided regions connected in parallel to the number of divided regions of N-channel and P-channel MOS type transistors according to the load capacitance. 3. The semiconductor device according to claim 2, wherein the semiconductor device is formed by changing the number while keeping the number constant.