JPH03280294A - Memory cell circuit for semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To remove useless transistors (TRs) on a gate array and to easily execute layout design by using the same number of N-channle MOS TRs and P-channel MOS TRs. CONSTITUTION:The above memory cell circuit consists of two inverter circuits 1a, 1b, two N-channel MOS TRs 2a, 2b and two P-channel MOS TRs 3c, 3d and the outputs of respectively inverter circuits 1a, 1b are mutually connected to the inputs of the other inverters 1b, 1a to constitute a data holding loop. The memory cell circuit can be constituted of four N-channel MOS TRs and four P-channel MOS TRs. Thereby, when a word line, the inverse of WL2, is set up to an 'L' level, the P-channel MOS TRs 3c, 3d are turned on and data are read out to bit wire pair BIT2, the inverse of BIT2.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory cell circuit constituting a RAM of a semiconductor integrated circuit device.

[Conventional technology]

An example of a conventional memory cell circuit of this type is shown in FIG. 3 and will be described. This memory cell is dual baud) RAM
As shown in FIG. 3, inverter circuits 1m and 1b and N-channel MOS
It is composed of transistors 2m, 2b, 2c, and 2d. In this case, each of the inverter circuits ta and tb has its output connected to the input of the other to form a data holding loop. For example, if the output of the inverter circuit 1a is at fLJ level, the input of the inverter circuit 1b is I
If it is at LJ level, its output will be at rHJ level. As a result, the input of the inverter circuit 1a is at the IHJ level, and its output is at the fLJ level. In this way, data can be held without any contradiction.

Also, two N-channel MO8) Langimeta 2 凰.

The gates of the transistors 2b and 2b are commonly connected to the word line WL1. At this time, when word a■,1 is set to "H" level, N channel MOS transistors 2m, 2
b is not in the ON state, and the data held by the inverter loop circuit is on the bit line bare BIT1. Read out to BITt.

Also, two N-channel MOS transistors 2c.

The gates of 2d are commonly connected to the word line WL2. At this time, the word line 'wL2 is rHJ
When set to level, N channel MOS transistor 2
c and 2d are not in the ON state, and the data held by the inverter loop circuit is the bit line bare BIT2, BIT2.
is read out.

On the other hand, since an inverter circuit is usually constructed from a pair of P-channel MOS transistors and N-channel MOS transistors, the circuit shown in FIG. 3 can be expressed as a transistor-level circuit as shown in FIG. 4. In Figure 4, 2., 2
f is each inverter circuit 1a.

One of the N-channel MOS transistors configuring 1b is F), 3e, and 3f are the same inverter circuit 11°1b.
This is the other P-channel MOS transistor constituting the transistor.

As shown in FIG. 4, the conventional memory cell circuit consists of six N-channel MOS transistors and two P-channel MOS transistors.
It will be composed of S transistors.

By the way, when considering configuring this memory cell circuit on a gate array, this circuit configuration is extremely disadvantageous. The structure of the gate array will be explained with reference to FIGS. 5 to 7.

FIG. 5 is a plan view of a semiconductor integrated circuit device equipped with a gate array. In the figure, 4 is a semiconductor chip, 5 is an input/output pad, and 6 is a basic cell stage. 6 is an enlarged plan view showing the basic cell stage 6 of FIG. 5. FIG. Here, as an example of the basic cell stage 6, one of a gate separation type is shown. In FIG. 6, 7a is a P-type diffusion region, and 7b is an N-type diffusion region, which correspond to the source or drain of a P-channel MOS transistor and the source or drain of an N-channel MOS transistor, respectively. 8m and 8b are P channel and N channel MO respectively
This is the gate of the S transistor. FIG. 7 is an equivalent circuit diagram of the basic cell stage 6 in FIG. 6, in which 91 is a P-channel MOS transistor and 9b is an N-channel MOS transistor.
These transistors 9m and 9b are S transistors.
are connected in series. In the gate isolation type basic cell stage 6, the series-connected transistors are separated by turning off the transistor at the position to be separated, and a desired circuit is constructed using the separated transistors.

In this way, in this type of gate array, N-channel MO
There are the same number of S transistors and P channel MOS transistors.

[Problem to be solved by the invention]

The conventional mesoricell circuit described above has six N-channel M
Since it is composed of an OS transistor and two P-channel MOS transistors, there are four P-channels on the gate array.
There is a problem in that channel MOS transistors are wasted if they are not used9.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a memory cell circuit that can efficiently configure dual portability on a gate array.

[Means to solve the problem]

The memory cell circuit according to the present invention uses a P-channel MOS transistor instead of an N-channel MOS transistor connected to one bit line bare of the memory cell, and the memory cell is constructed with the same number of P-channel and N-channel yIDS transistors. This is how it is configured.

[Effect]

According to the present invention, the memory cell circuit is configured into four N-channel M
It can be configured with an O8 transistor and four P-channel MOS transistors (same number of P/N transistors), so
When configuring a memory cell circuit with a gate array, there are many unnecessary transistors.

〔Example〕

FIG. 1 is a configuration diagram of a memory cell circuit showing one embodiment of the present invention. As shown in FIG. 1, the memory cell circuit of this embodiment includes two inverter circuits 1m and 1b, two N-channel S transistors 21.2b, and two P-channel YDS transistors 3c.

3d, each inverter circuit 11, 1b connects the output to the input of the other to form a data holding loop. and one N-channel MoS transistor 2
The drain of & and the drain of P channel yDS transistor 3c are each inverter circuit 1m.

The drain of the other N-channel MOS transistor 2b and the drain of the P-channel MOS transistor 3d are connected to the other input/output connection point p2 of each inverter 1m, 1b. ing. Also, the gate of N-channel MOS transistor 2& is connected to the gate of N-channel MOS transistor 2b and connected to one word line WLl, and P
The gate of channel MOS transistor 3C is connected to the gate of P channel MOS transistor 3d, which in turn is connected to the other word line WL. Furthermore, the sources of N-channel and P-channel MOS transistors 2m and 3e are connected to bit lines BIT1. connected to BIT,
N-channel and P-channel MOS transistor 2b.

Each source of 3d is connected to a bit line BIT, , BI
T.

It is connected to the. Note that FIG. 2 is a transistor-level equivalent circuit of the circuit in FIG. 1, and the same reference numerals in the figure indicate the same or equivalent parts.

As described above, according to this embodiment, the N-channel MOS transistor 2c forms part of the memory cell circuit.

By using P-channel MOS transistors 3c and 3d instead of 2d (2 and 3), the memory cell circuit can be made up of four N-channel MOS transistors, as shown in FIG.
) transistor and four N-channel MOS ) transistors.

Therefore, when the word line WL2 is set to the rLJ level, the P channel MOS transistors 3c and 3d are not in the ON state, and the bit line pair BIT2 and BITxK data are read out.

Note that the present invention is not limited to the above-mentioned embodiments.
It can also be constructed using transistors that constitute the basic cell of /A.

〔Effect of the invention〕

As described above, since the memory cell circuit according to the present invention uses the same number of N-channel MOS transistors and P-channel MOS transistors, the memory cell can be configured without unnecessary transistors on the gate array.

Furthermore, the memory cell circuit according to the present invention is applicable not only to gate arrays but also to general RAMs.

That is, even in the case of a general RAM, according to the memory cell circuit of the present invention, since the same number of MOS transistors are used for P and N channels, it is only necessary to arrange the transistors in an orderly manner like a gate array, and the layout design is easy. There is an effect.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a memory cell showing an embodiment of the present invention;
Figure 2 is a transistor-level circuit diagram of the circuit in Figure 1, Figure 3 is a circuit diagram of a conventional memory cell, Figure 4 is a transistor-level circuit diagram of the circuit in Figure 3, and Figure 5 is a gate-level circuit diagram. FIG. 6 is an enlarged plan view showing the basic cell stage of FIG. 5, and FIG. 7 is an equivalent circuit diagram of the basic cell stage of FIG. 6. 1B, 1b++ *e *Inverter circuit, 2m, 2
b. 2s, 2f ・Q@ΦN channel MOS transistor,
3c, 3d, 3e, 3fa @ 1111 P channel MOS transistor, WL, , wL, 21+ 11
e II 7-dore, BIT! .

Claims (1)

[Claims] first and second inverter circuits, first and second N-channel MOS transistors, and first and second P-channel M
The first and second inverter circuits each have an output connected to the input of the other to form a data holding loop, and the drain of the first N-channel MOS transistor and the first P-channel MOS transistor are connected to each other. The drain of the transistor is connected to the input/output connection point of one of the first and second inverter circuits, and the drain of the second N-channel MOS transistor and the drain of the second P-channel MOS transistor are connected to the input/output connection point of one of the first and second inverter circuits. Connected to the other input/output connection point of the circuit, the gate of the first N-channel MOS transistor is connected to the gate of the second N-channel MOS transistor, and the gate of the first P-channel MOS transistor is connected to the gate of the second N-channel MOS transistor. A memory cell circuit of a semiconductor integrated circuit device, characterized in that the memory cell circuit is connected to the gate of a P-channel MOS transistor.