JPS62217494A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To disuse a power feed line and to improve the degree of integration of a semiconductor memory device by connecting word lines, transfer gates, and flip-flops. CONSTITUTION:A semiconductor memory device 1 consists of plural word lines 2, plural couples of bit lines 3 and 4, and plural memory cells 5, and the cells 5 each consist of a flip-flop 51, and transfer gates Q52 and Q53. The lines 2, the gates of the transfer gates Q52 and Q53, and power terminals 51a and 51b of the flip-flops 51 are connected, and the sources S of the transfer gates Q52 and Q53 are connected to the lines 3. When no cell 5 is selected, the flip-flop 51 operates with electric power supplied from the line 2 and when a cell 5 is selected, the flip-flop 51 operates by being powered on through the line 3. Thus, there is no special feed line required, so the degree of integration of the device 1 is improved.

Description

[Detailed Description of the Invention] [Summary] The present invention includes a plurality of word lines, a plurality of pairs of bit lines, and a plurality of memory cells connected to each of the word lines and the multiple pairs of bit lines. The memory cell includes a pair of flip-flops each having a transistor of one conductivity type, and a pair of transfer gates each including a transistor of the opposite conductivity type to the transistor of the flip-flop, is connected to the gate of the transfer gate and the power supply terminal of the flip-flop, thereby making it possible to eliminate the need for a power supply line and improve the degree of integration of the semiconductor device 1.a.

[Industrial application field]

The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a plurality of word lines, a plurality of bit lines, and a plurality of memory cells connected to each word line and the multiple pairs of bit lines.

[Conventional technology]

FIG. 2 is a circuit diagram showing an example of a conventional semiconductor memory device.

The conventional semiconductor memory device 11 includes a plurality of glue-1 cotton 12,
It has a plurality of pairs of bit lines 13 and 14 and a plurality of memory cells 15 connected to each of these word lines 12 and multiple pairs of pin 1-lines 13 and 14. Further, each memory cell 15 is composed of a flip-flop 151 and a pair of transfer gates Q, 5□ and Q, . . . each consisting of an n-type Mis) transistor.

The flip-flop 151 has a pair of cross-connected n
Type MTS transistor Q, 6. , and Q, 9. □ and
The transistor Q, 7. ．． and a pair of resistance elements RIS+3 and RIS+4 provided between each drain of QISI2 and the power supply line 16, respectively. This flip-flop 151 has a power supply voltage of ■.

Flip-flop 1 is connected to the power supply line 1G which is given
51 are connected by power terminals 151a and 152a,
This allows it to receive power and hold stored data. For example, when reading data stored in the flip-flop 151, a high level signal is applied to the word line 12 and two transfer gates are connected.
) Open the gates of Q152 and Q,53. Then, the potential state of the transistors Q Hs 1 + and Q8,1□ in the flip-flop 15 is changed to the respective transfer gates Q1, 2 and Q, 5 . jm and appears on a pair of bit lines 13 and 14. The potential states of bit lines I3 and +4 are further amplified by an external read amplifier (not shown) and taken out as an output.

In the above, the power to the flip-flop 151 is always supplied from the power supply line 16.

[Problem that the invention seeks to solve]

'', the conventional semiconductor memory device 11 includes a plurality of word lines 12, a plurality of pairs of bit lines 13 and 14,
4) A plurality of memory cells 15 are provided, but a power supply line 16 must be further provided for supplying power to the flip-flops 15 of each memory cell 15.

Incidentally, in order to improve the degree of integration of a semiconductor memory device, it is advantageous to reduce the number of elements and wiring, but since the conventional semiconductor memory device 11 requires a power supply line 16, it is difficult to integrate it. This has become an impediment to improving the level of performance.

In view of the above-mentioned problems, the present invention uses a memory cell comprising a flip-flop having a pair of transistors of one conductivity type, and a pair of transfer gates comprising a transistor of the opposite conductivity type to the transistors of the flip-flop. The present invention aims to improve the degree of integration of a semiconductor memory device by connecting a word line to the gate of the transfer gate and the power supply terminal of the flip-flop, thereby eliminating the need for a power supply line.

[Means for solving problems]

According to the present invention, a plurality of word lines 2, a plurality of pairs of bit lines 3 and 4, each word line 2 and the multiple pairs of bit lines 3,
and a plurality of memory cells 5 connected to the semiconductor device 1. a device 1, in which each of the memory cells 5
is a pair of cross-connected transistors Q5 of one conductivity type.
A flip-flop 51 with an eye and a transistor Q512, and transistors Q511 and Q of the flip-flop 51.
transistors Q, 11 and Q5□ of the flip-flop 51 are connected to the bit lines 3 and 4 and the bit lines 3 and 4;
A pair of transfer gates Q5□ and Q6. and the word line 2 is connected to the transfer gates C15z and Q53.
gate and the power supply terminal 5 of the flip-flop 51
A semiconductor memory device 1 is provided which is connected to 1a and 51b.

[For production]

According to the semiconductor memory device of the present invention having the above configuration,
When a memory cell consisting of the following memory cells is not selected, power is supplied from the word line to the flip-flop of the memory cell;
Further, when the memory cell is selected, the transfer gate is connected to the transfer gate from the pair of bit lines at the read state voltage (power is supplied to the flip-flop, and the data stored in the flip-flop is held).

Therefore, a power supply line is not required, and the degree of integration of the semiconductor memory device can be improved.

〔Example〕

Embodiments of a semiconductor memory device according to the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of a semiconductor memory device according to the present invention.

The semiconductor memory device 1 includes a plurality of word lines 2, a plurality of pairs of bit lines 3 and 4, and a plurality of memory cells 5 connected to each word line 2 and the multiple pairs of bit lines 3 and 4. .

Each memory cell 5 includes a flip-flop 51 and a p-type MT.
S) A pair of transfer gates Q5 consisting of transistors
□ and Q53.

The flip-flop 51 includes a pair of cross-connected n-type M
IS) transistors Q511 and Q51□ and the transistors Q51. and Q5. , a pair of resistance elements R provided between each F'l/in of , and the word line 2.
513 and R5I4.

One end of the resistance element R113 is connected to the word line 2 through the power supply terminal 51a of the flip-flop 5I, and the resistance element R113
The other end of 313 is the drain of transfer gate) Qsz,
It is commonly connected to the drain of transistor Q511 and the gate of transistor QsI2. Similarly, one end of the resistive element R5, 4 is connected to the power supply terminal 5 of the flip-flop 51.
1b to word line 2, and resistor element R614
The other end is the train of transfer gate QS3, the drain of transistor QSI2, and the transistor Q511.
are commonly connected to the gates. Here, a low level voltage VS3 is applied to the sources of transistor 05 and Q5I□, respectively.

The gate of transfer gate Q,2 is connected to word line 2, and the source of transfer gate Q5□ is connected to bit line 3.Similarly, transfer gate Q
The gate of 5□ is connected to the word line 2, and the source of the transfer gate QS3 is connected to the bit line 4.

Next, the operation of the above-described semiconductor device will be explained.

First, when the memory cell 15 is not selected, a high-level signal equal to the power supply voltage VDD is applied to the word line 2, and the transfer gates Q, 2, and QS3 are in a cutoff state, but the flip-flop 51 is in a cut-off state. Power will be supplied from word line 2. That is, the power supply voltage VDn (high level signal) applied to the word line 2 is
Resistance element R1 connected to word line 2 through power supply terminal 51a
1I3 and word line 2 through a resistive element R5I4 connected to the power supply terminal 51b, two transistors Q,
and Q, 12. When the memory cell 15 is not selected, the flip-flop 51 retains its stored data by the power supplied from the word line 2.

Next, when the memory cell 15 is selected, a low level signal of the voltage VS3 is applied to the word line 2, and the transfer gates Q5□ and Q5. is in the on state. At this time, the flip-flop 51 cannot receive power from the word line 2, but the memory cell 1
5 is selected, transfer gates Q5□ and Q53 are on, and the voltage applied to the pair of bit lines 3 and 4 is applied to the transistors Q and 1.
1 and Q51□. That is, the read voltage applied to the pair of bit lines 3 and 4 is applied to the bit lines 3 and 4 through the transfer gate Q, 2 connected to the bit line 3 and the transfer gate Q, 3 connected to the bit line 3.
two transistors Q5□ and Q5. . supplied to

When the memory cell 15 is selected, the flip-flop 51 retains its stored data by power supplied from the pair of bit lines 3 and 4.

In the above embodiment, the transfer gates QS2 and QSI of the memory cell 5 are connected to the p-type MIS transistor Q.
, 1. Although the transfer gates Q, 2 and Q, 1□ of the memory cell 5 have been described as n-type Mis) transistors,
and QS3 are n-type MIS transistors, and transistors Q5□ and Q5 of the flip-flop 51,
2 can also be a p-type MISI-transistor.・
2, the power supply voltage VD is supplied to the drains of the p-type MTS transistors QSI! high level signal)
must be configured so that it is applied.

Furthermore, as is conventionally known, the resistive elements R513 and R5,4 of the flip-flop 51 are not resistive elements (for example, high-resistance polycrystalline silicon resistors), but are transistors (for example, depletion type MIS transistors). It goes without saying that you can.

(Effects of the Invention) As described above in detail, the semiconductor memory device according to the present invention includes a flip-flop including a pair of transistors of one conductivity type, and a transistor of the opposite conductivity type to the transistor of the flip-flop. By using a memory cell having a pair of transfer gates and connecting a word line to the gate of the transfer gate and the power supply terminal of the flip-flop, the degree of integration of the semiconductor memory device is improved by eliminating the need for a power supply line. be able to.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a semiconductor memory device according to the present invention, and FIG. 2 is a circuit diagram showing an example of a conventional semiconductor memory device. DESCRIPTION OF SYMBOLS 1...Semiconductor memory device, 2...Word line, 3.4...Bit cotton, 5...Memory cell, 51...Flip-flop, Q5□, Q5. ...Transfer Gate, Q5. ,,
Q... ...transistor, Rs+1. Rs+a・
...Resistance element.

Claims (1)

[Scope of Claims] 1. A semiconductor memory device having a plurality of word lines, a plurality of pairs of bit lines, and a plurality of memory cells connected to each word line and each pair of bit lines. Each of the memory cells includes: a flip-flop including a pair of cross-connected transistors of one conductivity type; the transistors of the flip-flop are connected to the bit line, and the transistors of the flip-flop are of an opposite conductivity type; a pair of transfer gates made of transistors, wherein the word line is connected to a gate of the transfer gate and a power supply terminal of the flip-flop.