JPS61243996A - Readout/write circuit for ram - Google Patents

Abstract

PURPOSE:To convert a readout/write speed of the titled circuit to a high speed, and also to make its constitution simple and small in size by providing a readout/write switch on an input side of an inverter for forming a sense amplifier. CONSTITUTION:Switches S1, S2 which have been provided on input sides of inverters I1, I2 which are connected to a pair of bit lines 11, 12 respectively and form a sense amplifier are controlled by a signal from a control signal terminal, and readout of a RAM is executed through data output terminals 17, 18. This readout is executed at a high speed since the switches S1, S2 are provided on the input sides whose parasitic capacity is small and which are not influenced by an on-resistance, and the time constant is small. In the same way, input data from terminals 13, 14 are amplified by the sense amplifier through switches S3, S4 and written at a high speed on the RAM. According to them, a readout/write speed is converted to a high speed, and also a write amplifier is not required, and the constitution becomes simple and small in size.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application IF) The present invention relates to a read/write circuit for RAM that is faster and more compact.

(Summary of the Invention) Invention Ring 1: In a RAM read/write circuit for reading and writing data to and from a bit line of a memory cell, conventionally, a bit line and a sense amplifier or a bit line are connected at the time of reading or writing. The operation delay caused by the on-resistance of the switch connected to the write circuit has been eliminated by providing the switch on the input side of the inverter that constitutes the sense amplifier and in the feed pack loop. By sharing the write circuit and the write circuit, the structure is simplified and the size is reduced.

(Prior Art) FIG. 3(a) shows the configuration of a conventional RAM read/write circuit, in which reference numerals 11 and 12 are bit lines connected to memory cells. Note that mutually complementary data signals are input and output to the bit lines 11 and 12. I
,, I2 are input terminals constituting a flip-flop type sense amplifier, and their input terminals and output terminals are connected to each other, and the inverters I1. The output terminals of I2 are connected to data output terminals 17, 18, respectively, and switches S1. S2 are connected to bits sll, 12, respectively. Note that mutually complementary data appears at the data output terminals 17 and 18. On the other hand, 13
, I4 is an inverter constituting a write circuit, whose input terminals are connected to the data input terminals 13 and 14 for writing, and whose output terminals are connected to the bits 11 and 12 via switches S, , S4. In addition, data input terminal 1
3.14 has mutually complementary beliefs.

A number is given. In addition, 16 is a switch S,
, S, control signal terminals 15 are eight switches.

This is the control signal terminal of S4, and when reading, switch S
,, S2 is on and switch S3 . S4 becomes ear, and when writing, switch S1. A control signal is given so that S2 is off and switches S, , S, are on.

FIG. 3(b) shows FIG. 3(a) more specifically, in which M1 and M3 are transistors constituting inverter 2, and M 21 M a is a transistor constituting inverter r2. Furthermore, the transistor M1. M2
One end of is connected to power supply terminal 1, and transistors M, , M
One end of transistor M4 is connected to the ground line via transistor M5, and a signal applied to control signal terminal 19 can control on/off of transistor M, thereby controlling the operation of the sense amplifier. The other parts are the same as those in FIG. 3(a).The same parts are given the same reference numerals.

The operation will be explained below. In addition, just before operation, bit line 1
It is common to precharge so that the potential difference between 1.12 and the sense amplifier output terminals are both Ov.

Therefore, in the read operation, the control terminal 19
is set to low level, the transistor M5 is turned off to prevent the power supply current from flowing to the sense amplifier made up of transistors M to M, and the switches S, S2 are turned on to transfer the potential difference that the memory cell gives to the bit lines 11 and 12 to the sense amplifier. tell. Then, when an output signal from 911.12 is generated between the output terminals of the sense amplifier, the control signal terminal 19 is set to a high level and the transistor M is turned on.

Then, since the flip-flop type sense amplifier is a positive feedback amplifier, this potential difference is amplified, and finally, depending on the read data, one of the data output terminals 17 and 18 is set to the ground level and the other to the power supply potential. do.

In addition, during writing, the switches S3 and S4 are turned on, and the write data applied from the data input terminals 13 and 14 is transferred from the inverter I3 and I4 to bit $.
11.12 and is written.

(Problems to be Solved by the Invention) Although the conventional circuit shown in FIG. 3 operates as described above, it has the following drawbacks. That is, FIG. 4 shows an equivalent circuit during each operation of the circuit in FIG. 3(a), with (a) showing the read operation and (b) the write operation. Yes, but
During reading, switch S1 is activated as shown in (a).
The on-resistance of ゜S2 will be placed between bit 4911.12 and the output terminal of inverter 11゜I2, and
During writing, switch S3 is activated as shown in (b).
．． The on-resistance of S4 is between bit line 11.12 and inverter I.
3. It will be inserted between it and the output terminal of I4. In general, a MOS (MOS) transistor has a large on-resistance, so in this type of circuit that uses it as a switch, the time constant with the output capacitance of the sense amplifier becomes large, and the potential at the output point of the sense amplifier is delayed. This was causing speed deterioration. Furthermore, during writing, the time constant between the on-resistance of the switches S3j and the bit line parasitic capacitance similarly becomes an obstacle to increasing the writing speed.

(Means for Solving the Problem) The present invention aims to eliminate the above-mentioned drawbacks. and sense amplifier feedback loop, eliminating deterioration in operating speed due to switch on resistance and speeding up reading and writing.
Furthermore, another object of the present invention is to provide a read/write circuit for a RAM that can reduce the driving capability of a drive element of a data input terminal by using a sense amplifier as a write circuit during writing, and can be made smaller by omitting the write circuit. .

Hereinafter, the present invention will be described in detail with reference to the drawings showing examples.

FIG. 1(a) is a basic configuration diagram showing an embodiment of the present invention, and FIG. 1(b) is a circuit diagram specifically constructed using MOS transistors. In Figure 1, 1 is a power supply terminal;
1.12 are bit lines, 13.14 are data input terminals for writing, 17.18 are data output terminals, and bit lines 11.12. Data input terminals 13.14. Complementary signals are applied or generated to the data output terminals 17 and 18, respectively.

In FIG. 1(a), the output terminal of inverter I is connected to one bit line 11 and one data output terminal 17, and is also connected to the input terminal of inverter I2 via switch S2. The output terminal of the inverter I is connected to the other bit cotton 12 and the other data output terminal 18, and the switch S is connected to the input terminal of the inverter I.
1. Further, one data input terminal 13 is connected to the input terminal of the inverter via the switch S3, and the other data input terminal 14 is connected to the input terminal of the inverter E through the switch S3.
4 to the input terminal of the inverter I2. Note that 15.1B is a control signal terminal that controls the on/off of switches S□ to S4.
,, S2 is turned on and switch S3 . S4 is turned off, and at the time of writing, switches S, , S2 are turned off, and switches S3 . A control signal is given to turn on S4.

In FIG. 1(b), M, , M3 are transistors forming the inverter 1, and M22M4 is a transistor forming the inverter I2. Also, the transistor Ml
, M2 is connected to the power supply terminal 1, and the transistor M
3. One end of M4 is connected to the ground line via a transistor M5, and a signal applied to a control signal terminal 19 controls turning on and off of the transistor M5, thereby controlling the operation of the sense amplifier.

In operation, the control signal terminal 15 is
．． Switches S, S2 are turned on by the control of 16,
Switch S3. If S4 is turned off, inverter I1
．． The input and output terminals of I and I are connected to each other to form a flip-flop type sense amplifier, and the bit! It is possible to read the level of s11.12 and output it to output terminals 17.18. Furthermore, when writing, if the switches S, , S2 are turned off and the switches S, , S4 are turned on under the control of the control signal terminals 15, 16, the inverters I, , I can operate independently, and data input is possible. Data is written by inverting the signals applied to terminals 13 and 14 and applying them to bit lines 11 and 12.

Fig. 2 shows an equivalent circuit during each of the above operations. During reading, as shown in (a), the bit lines 11 and 12 are directly connected to the output terminal of the inverter 1°I2, and the switch Sl.

Since the switch S2 has a small parasitic capacitance and is provided on the input side which is not affected by the on-resistance, the switch S1. There is no speed deterioration due to the time constant caused by the on-resistance of S2, and the read speed can be increased. Also, during writing, as shown in (b), an inverter I operates as a write amplifier.
4. The output terminal of I2 is connected directly to the bit line 11.12 and is further connected to the switch S3. Since S4 is provided on the input side of the sense amplifier, the time constant between the input capacitance and on-resistance of the sense amplifier is small, so that the sense amplifier can be set quickly.
The 14 driving elements are inverters I that constitute a sense amplifier.
It is sufficient to drive the gates of the transistors in the 12 input stages, so there is an advantage that a large amount of driving power is not required. In other words, in a sense amplifier circuit, the size of the transistor is usually large for high-speed operation, and the current for inverting the memory cell is passed through the inverters I, , I.
2 can be sufficiently supplied. Therefore, in the conventional circuit, data input terminals 13 and 14 are used for writing.
Normally, an inverter for a write circuit having a large driving capacity is provided, but the present invention does not require a write circuit, and has the advantage of being able to be miniaturized by reducing the number of elements.

(Effects of the Invention) As described above, in the present invention, by removing the switch that was conventionally inserted between the output of the sense amplifier or write circuit and the bit line, Because there is no speed deterioration due to the time constant,
reading.

This has the effect of speeding up writing. Further, since a write circuit is not required, there is an effect that the circuit can be made smaller.

[Brief explanation of drawings]

Figure 1 shows an embodiment of the present invention, (a) is a basic configuration diagram, (b) is a specific circuit configuration diagram composed of MOS transistors, and Figures 2 (a) and (b) are Fig. 1(a) is a schematic diagram of both the read and write operations, and Fig. 3 shows a conventional circuit example, (a) is a basic configuration diagram, and (b) is a MOS transistor. FIGS. 4(a) and 4(b) are schematic circuit diagrams for the reading and writing operations shown in FIG. 3(a), respectively. 11, 12...Bit line, 13.14...
...Data input terminal, 15.18.19...Control signal terminal, 17.18°°. ...Data output terminal, 1...Power supply terminal, 11
．． 12...Inverter, S1-S4...
Switch, Ml~M...transistor and 1 other person Figure 1 (b) Figure 2 (a) Figure 3 (a)

Claims (1)

[Claims] A RAM readout device that is connected to a pair of bit lines, reads the bit line signal and outputs it to a pair of data output terminals, and also provides a write signal to the bit line based on the signal given from a pair of data input terminals. The write circuit includes first and second inverters and first to fourth switches, and the output terminal of the first inverter is connected to one bit line and one data output terminal, and the output terminal of the second inverter is connected to one bit line and one data output terminal. the input terminal via the second switch, the output terminal of the second inverter is connected to the other bit line and the other data output terminal, and the input terminal of the first inverter is connected via the first switch. one data input terminal is connected to the input terminal of the first inverter through the third switch, and the other data input terminal is connected to the input terminal of the second inverter through the fourth switch. , the first and second switches are turned on and the third and fourth switches are turned off during reading, and the first and second switches are turned off and the third and fourth switches are turned off during writing.
A read/write circuit for a RAM, characterized in that a control signal is applied to turn on a switch of a RAM.