JP2544802B2 - Semiconductor device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device including two or more MOS differential amplifier circuits to which a bit line pair is gate-input and drain outputs are commonly connected.

[Conventional technology]

Conventional CMOS static RAM (Random Access Memor
As an example of the differential amplifier circuit of y), a circuit as shown in FIG. 2 has been used. Although FIG. 2 shows an example of 2 bits for convenience, the basic structure is the same even if the number of bits is increased.

In FIG. 2, 201 and 204 are memory cells, 202 and 205 are bit line precharge circuits, and 203 is an N-type MOS transistor 20.
A differential amplifier circuit composed of 8,209,210, 206 is a differential amplifier circuit composed of N-type MOS transistors 211,212,213, SE
1, SE2 is the selection signal of the differential amplifier circuit, BL1, ▲ ▼, BL2,
▲ ▼ is a bit line, W _L is a word line, DB, ▲ ▼ are common output lines of the plurality of differential amplifier circuits 203 and 206, and 207 is a load circuit of the common output line DB, ▲ ▼.

The conventional circuit operation will be described with reference to the operation waveform diagram of FIG.

When the precharge start pulse φ _P falls at time t _o , all the bit lines BL1, ▲ are set by the precharge circuits 202 and 205.
▼, BL2, ▲ ▼ are precharged, and at the same time, the potential of the common output line DB, ▲ ▼ is balanced by the load circuit 207. At the precharge completion time t ₁ , when the word line W _L rises with the rise of the precharge start pulse φ _P , one of the bit lines slowly lowers the level by driving the memory cells 201 and 204. When the selection circuits SE1 of the differential amplifier circuit 203 rises to time t _2, the
The differential amplifier circuit 203 is selected, and the bit line BL1, ▲ ▼
The potential level of one of the common output lines DB, ▲ ▼ is lowered by the MOS transistors 208 and 209 which receives the input, and information is transmitted to the next stage circuit. On the other hand, at this time, the selection signal SE2 other than the selection signal SE1 does not rise, and the MOS transistor 213 is not driven, so that the differential amplifier circuit 206 is in the non-selected state.

[Problems to be Solved by the Invention]

The conventional differential amplifier circuit described above has the following drawbacks because the outputs of the plurality of differential amplifier circuits are commonly connected.

In the circuit of FIG. 2, after the precharge, the selection signal SE
When the differential amplifier circuit 203 is selected by the rise of 1,
The slight potential difference between the bit lines BL1 and ▲ ▼ causes a difference in the conductances of the MOS transistors 208 and 209 to amplify the common output line DB and ▲ ▼. On the other hand, the MOS transistor 213 of the non-selected differential amplifier circuit 206 is kept in the non-conductive state because the selection signal SE2 is “LOW”, and the potential V _{B of the} node _B is the charging potential at the time of precharging. It is a level.
The potential V _B is between the threshold voltage V _T of the MOS transistors 211, 212 and the bit line potential V _BL2 , V ▲ ▼, and V _B > V _BL2 −V _T
If the relationship of V _B > V ▲ ▼ −V _T is satisfied, the MOS transistors 211 and 212 maintain the non-conducting state. In this case, the differential amplifier circuit 203 quickly performs the amplification operation without being affected by the other non-selected differential amplifier circuit 206.

However, when the potential V _B of the node B of the non-selection differential amplifier circuit 206 has a relation of V _B ≦ V _BL2 −V _T or V _B ≦ V ▲ ▼ with respect to the bit line potentials V _BL2 and V ▲ ▼, the non-selection The MOS transistor 211 or 212 of the selected differential amplifier circuit 206 becomes conductive, which hinders the amplifying operation of the selected differential amplifier circuit 203.

For example, the MOS transistor 211 of the unselected differential amplifier circuit 206,
When both 212 are in the conductive state, the data of the common output line DB, ▲ ▼ amplified by the selected differential amplifier circuit 203 is canceled and the amplifying operation is delayed. Further, even when either one of the MOS transistors 211 and 212 becomes conductive, the differential amplifier circuit 203 capable of amplifying a minute signal is
The load capacity of the node B can be seen from either one of the common output line DB, ▲ ▼, and the capacity of the common output line DB, ▲ ▼ originally designed symmetrically is unbalanced,
The amplification operation of the differential amplifier circuit 203 is delayed.

Therefore, when designing a differential amplifier circuit, V _B
The dimensions of the load circuit 207 and the differential amplifier circuit must be determined so as to satisfy the relationship of> V _BL2 −V _T and V _B > V ▲ ▼ −V _T. In this case, variations in the manufacturing process of MOS transistors must be taken into consideration, and there is a drawback that circuit design is extremely difficult.

It is an object of the present invention to provide a semiconductor device having a differential amplifier circuit that improves such a defect and performs a stable amplification operation without being affected by a non-selected differential amplifier circuit.

[Means for solving the problem]

A semiconductor device according to the present invention includes first and second N-type MOS transistors in which first and second bit lines forming a bit line pair are gate-connected, and sources are commonly connected.
First and second differential amplifier circuits comprising first and second N-type MOS transistors and a third N-type MOS transistor connected between the ground and a gate to which a selection signal for activating the circuit is applied The first N-type of the first and second differential amplifier circuits including
In a semiconductor device in which drains of a MOS transistor and drains of a second N-type MOS transistor are connected to each other and a common output line is connected to these connection lines, first and second N-types of each differential amplifier circuit are provided. A P-type MOS transistor whose gate input is a selection signal in phase with the selection signal is connected between the common source of the MOS transistor pair and the power supply.

[Action]

The differential amplifier circuit holds the non-selected state by setting both selection signals to the low level. In this state, the potential of the node of the non-selected differential amplifier circuit is kept at V _{DD because the} P-type MOS transistor becomes conductive. Be drunk

Therefore, the first and second N-type of the non-selected differential amplifier circuit
MOS transistors never reach perfect conduction,
It does not hinder the amplification operation of the selected differential amplifier circuit.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram in which the present invention is applied to a read system circuit of a static RAM having a CMOS transistor structure.

In FIG. 1, 101 and 104 are memory cells, 102 and 105 are bit line precharge circuits, 103 and 106 are differential amplifier circuits, and 107.
Is a load circuit for the common output line DB, ▲ ▼ of the differential amplifier circuits 103, 106. The differential amplifier circuit 103 includes an N-type MOS transistor 109 which receives the selection signal SE1 as a gate input and a selection signal SE.
P-type MOS whose gate input is the selection signal SE11 in phase with 1
It is composed of a transistor 108 and N-type MOS transistors 110 and 111 whose gate inputs are the bit lines BL1 and ▲ ▼, and the transistors 108 to 111 are connected at a node a. The differential amplifier circuit 106 is an N-type MOS whose gate input is the selection signal SE2.
The selection signal that is in phase with the transistor 113 and the selection signal SE2
P-type MOS transistor 112 having SE22 as a gate input, and N-type MO having bit lines BL2 and ▲ ▼ as its gate inputs
Comprised of S-transistors 114 and 115, each transistor 112
~ 115 are connected at a node b. Further, the differential amplifier circuits 103 and 106 are connected by common output lines DB and DB. In the circuit having such a configuration, the differential amplifier circuit 103 is selected by the rising edge of the selection signal SE1 and the rising edge of the selection signal SE11. First, when the selection signal SE11 rises, P
Type MOS transistor 108 becomes non-conductive state, since then the MOS transistor 109 is turned by the selection signal SE1 and rise, the potential V _a of the node a falls, the common output line DB by MOS transistors 110 and 111, ▲ ▼ to The amplified data is output. On the other hand, the low level of the selection signal SE2 and the low level potential of the selection signal SE22 input the differential amplifier circuit 106 to hold the non-selected state. In this state, the potential V _b of the node b of the non-selected differential amplifier circuit 106 is kept at V _DD by the conduction of the MOS transistor 112.

Therefore, the MOS transistors 114 and 115 do not reach a completely conductive state, and even if the potential of the bit line BL2 or ▲ ▼ becomes the V _DD level, the MOS transistors 114 and 115 are almost in a non-conductive state. Does not interfere with the amplification operation of.

〔The invention's effect〕

As described above, according to the present invention, by arranging the P-type MOS transistor whose gate input is the selection signal of the same phase as the selection signal of the differential amplifier circuit, between the common source of the differential N-type MOS transistor pair and the power supply. The selected differential amplifier circuit has the effect of operating stably without being affected by the non-selected differential amplifier circuit, and also enables stable operation against variations in the manufacturing process of MOS transistors. Another advantage is that the design of the differential amplifier circuit can be facilitated.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a semiconductor device according to an embodiment of the present invention, and FIG.
FIG. 3 is a circuit diagram of a conventional example, and FIG. 3 is an operation explanation diagram of the circuit of FIG. 101,104 ...... Memory cell 102,105 ...... Bit line precharge circuit 107 ...... Differential amplification circuit load circuit 103,106 ...... Differential amplification circuit 108,112 ...... P-type MOS transistor 109-111,113-115 ...... N-type MOS transistor BL1, ▲ ▼, BL2, ▲ ▼ …… Bit line DB, ▲ ▼ …… Common output line SE1, SE11, SE2, SE22 …… Selection signal a, b …… Node

Claims (1)

(57) [Claims] 1. A first and a second N-type MOS transistor in which first and second bit lines forming a bit line pair are respectively gate-connected and sources are commonly connected, and first and second N-type MOS transistors. Third N-type transistor connected between the MOS transistor and the ground and having a gate applied with a selection signal for activating the circuit
A first N-type MOS transistor drain and a second N-type MOS transistor drain that include first and second differential amplifier circuits each including a MOS transistor. In a semiconductor device having a common output line connected to these connection lines, the selection signal is provided between the common source of the first and second N-type MOS transistor pairs of each differential amplifier circuit and the power supply. A semiconductor device to which a P-type MOS transistor having a gate input of an in-phase selection signal is connected.