JP2544801B2 - Semiconductor device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device including two or more MOS differential amplifier circuits in which bit line pairs are gate-inputted and drain outputs are commonly connected.

[Prior Art] FIG. 2 shows a static RAM (R
FIG. 3 is a circuit diagram of a conventional example of a read system circuit of an andom access memory), and FIG. 3 is its operation waveform diagram. For convenience, a 2-bit example is shown, but the basic circuit configuration is the same even if the number of bits increases.

In FIG. 2, 201 and 204 are memory cells, 202 and 205 are bit line precharge circuits, and 203 is an N-type MOS transistor 20.
A differential amplifier circuit composed of 8 to 210, a differential amplifier circuit 206 composed of N-type MOS transistors 211 to 213, DB, ▲
▼ is a common output line of the differential amplifier circuits 203 and 206, 207 is a common output line DB, a load circuit of ▲ ▼, BL1, ▲ ▼, BL2, ▲
▼ indicates a bit line, W _L indicates a word line, and SE1 and SE2 indicate selection signal lines of the differential amplifier circuits 203 and 206.

The circuit operation of FIG. 2 will be described with reference to the operation waveforms of FIG. When the precharge start pulse φ _P falls at time t _o , the precharge circuits 202 and 205 cause all bit lines B
L1, ▲, ▼ BL2, ▲ ▼ are precharged,
At the same time, the load circuit 207 also balances the potentials of the common output line DB, ▲ ▼. At the precharge completion time t ₁ , when the word line W _L rises with the rise of φ _P , _one of the bit lines slowly falls due to the driving of the memory cells 201 and 204. Then, at time t ₂ , the selection signal SE1 of the differential amplifier circuit 203
When bit rises, bit line BL1, ▲ ▼ is input
Common output line DB, ▲ ▼ by MOS transistor 208,209
One of the potentials falls, is amplified to the next stage, and information is transmitted.

[Problems to be Solved by the Invention] In the above-described conventional circuit, the outputs of a plurality of differential amplifier circuits are commonly connected, and therefore have the following drawbacks.

In the circuit of FIG. 2, after precharge selection signal SE1
When the differential amplifier circuit 203 is selected due to the rise of, the minute potential difference between the bit lines BL1 and
A difference is generated in the conductance of 8,209, and the common output line DB,
Amplify ▲ ▼. On the other hand, non-selected differential amplifier circuit
Since the selection signal SE2 is "LOW", the MOS transistor 213 of 206 is kept in a non-conductive state, and the potential V _{B of the} node _B is the charging potential at the time of precharging. The potential V _B is the MOS transistor 2
Bit line potential V _BL2 a threshold voltage of 11,212 as V _T, V ▲
For ▼, V _B ＞ V _BL2 −V _T and V _B ＞ V ▲ ▼ −V _T
If the relationship is satisfied, the MOS transistors 211 and 212 maintain the non-conducting state. Therefore, the differential amplifier circuit 203 is
The amplification operation is performed promptly without being affected by the other non-selected differential amplification circuit 206.

However, the potential V _B of the node B of the non-selected differential amplifier circuit 206
Is the bit line potential V _BL2 , V ▲ ▼, V _B ≤ V _BL2 −V _T
Alternatively, when V _B ≦ V ▲ ▼ −V _T , the MOS transistor 211 or 212 of the non-selected differential amplifier circuit 206 becomes conductive, which hinders the amplification operation of the selected differential amplifier circuit 203. .

For example, when both MOS transistors 211 and 212 are turned on, the common output DB amplified by the selected differential amplifier circuit 203, ▲
The data of ▼ is canceled and the amplifying action is delayed. Also,
Even when one of the MOS transistors 211 and 212 is turned on, the differential amplifier circuit 203 that handles a minute signal can see the capacitance of the node B from one of the common output lines DB and ▲ ▼, and is originally designed symmetrically. Common output line DB, ▲
The capacitance of ▼ becomes unbalanced, which delays the amplification operation of the differential amplification circuit 203.

Therefore, when designing a differential amplifier circuit, V _B > V
_The dimensions of the load circuit 207 and the differential amplifier circuits 203 and 206 must be determined so that _BL2- V _T and V _B > V ▲ ▼ -V _T are satisfied. This requires consideration of variations in the manufacturing process of MOS transistors,
Circuit design has the drawback of being very difficult.

An object of the present invention is to provide a semiconductor device having a differential amplifying circuit which improves such drawbacks and performs a stable amplifying operation without being affected by an unselected differential amplifying circuit.

[Means for Solving the Problem] The semiconductor device of the present invention is configured such that the first,
A circuit is connected to the gate between the first and second N-type MOS transistors whose gates are connected to the second bit lines and whose sources are commonly connected, and between the first and second N-type MOS transistors and the ground. A first N-type MOS transistor of the first and second differential amplifier circuits is included, which includes first and second differential amplifier circuits each including a third N-type MOS transistor to which an active selection signal is applied. In a semiconductor device in which drains and drains of a second N-type MOS transistor are connected to each other and a common output line is connected to these connection lines, a pair of first and second N-type MOS transistors of each differential amplifier circuit is provided. A fourth N-type MOS transistor whose gate input is a selection signal having a phase opposite to the selection signal is connected between the common source and the power source.

[Operation] The differential amplifier circuit holds the non-selected state by setting the selection signal to the low level and the antiphase selection signal to the high level.
In this state, the potential of the node of the non-selected differential amplifier circuit is V _DD − due to the conduction of the fourth N-type MOS transistor.
Kept at V _T.

Therefore, the first and second N of the non-selected differential amplifier circuit
The type MOS transistor does not reach a complete conductive state and does not interfere with the amplifying operation of the selected differential amplifier circuit.

Example Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram in which the present invention is applied to a read system circuit of a static RAM having a CMOS transistor structure.

In FIG. 1, 101 and 104 are memory cells, 102 and 105 are bit line precharge circuits, 103 and 106 are differential amplifier circuits, and 107 is a load circuit for the common output line DB, ▲ ▼ of the differential amplifier circuit. The differential amplifier circuit 103 includes an N-type MOS transistor 109 having SE1 as an input, an N-type MOS transistor 108 having ▲ ▼ as an input, and an N-type MOS transistor 108 having bit lines BL1 and ▲ as an input.
Type MOS transistors 110 and 111, each transistor
109 and 108 are connected at a node a. Differential amplifier circuit 106
Is an N-type MOS transistor 113 with SE2 as an input,
N-type MOS transistor 112 that inputs ▼, and N-type MOS transistor 11 that inputs bit line BL2, ▲ ▼
The transistors 113 and 112 are connected at a node b. The differential amplifier circuits 103 and 106 are connected by a common output line DB, ▲ ▼.

In the circuit having such a configuration, the selection of the differential amplifier circuit 103 is performed by the rising edge of the selection signal SE1 and the falling edge of ▼. First, the falling of ▲ ▼ brings the MOS transistor 108 into the non-conducting state, and then the rising of the selection signal SE1 brings the MOS transistor 109 into the conducting state.
The potential V _{a of the} node a falls, and the amplified data is output to the common output line DB, ▲ ▼ by the MOS transistors 110 and 111. On the other hand, the LOW level of the selection signal SE2, ▲
Differential amplifier circuit 106 by inputting High level of ▼
Holds the non-selected state. In this state, the potential V _b of the node b of the non-selected differential amplifier circuit 106 is the MOS transistor.
Conduction of 112 keeps it at V _DD −V _T. Therefore, the MOS transistors 114 and 115 do not reach a completely conductive state, and the potential of the bit line BL2 or ▲ ▼ is V _DD.
Even when the level is reached, it is as close as possible to the non-conducting state, so that the amplifying operation of the selected differential amplifier circuit 103 is not hindered.

As described above, according to the present invention, the N-type MOS transistor having the gate input of the signal opposite in phase to the selection signal of the differential amplifier circuit is arranged between the common source of the differential MOS transistor pair and the power supply. By doing so, the selected differential amplifier circuit has the effect of operating stably without being affected by the non-selected differential amplifier circuit, and is also stable against variations in the manufacturing process of the MOS transistor. This has the effect of enabling operation and facilitating the design of the differential amplifier circuit.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a semiconductor device according to an embodiment of the present invention, and FIG.
FIG. 3 is a circuit diagram of a conventional example, and FIG. 3 is an operation explanation diagram of the circuit of FIG. 101,104 …… Memory cell, 102,105 …… Bit line precharge circuit, 107 …… Bit line sense amplifier output load circuit, 103,106 …… Differential amplifier circuit, 108 to 115 …… N-type MOS transistor, BL1, ▲ ▼, BL2, ▲ ▼ …… bit line, DB, ▲ ▼ …… common output line, SE1, ▲ ▼, SE2, ▲ ▼ …… selection signal, a, b …… node.

Claims (1)

(57) [Claims] 1. A first and a second N-type MOS transistor in which first and second bit lines forming a bit line pair are respectively gate-connected and sources are commonly connected, and first and second N-type MOS transistors. Type N-type MO transistor connected between a MOS transistor and ground and having a gate applied with a selection signal for activating the circuit
A first N-type MOS transistor drain and a second N-type MOS transistor drain that include first and second differential amplifier circuits each including an S transistor. In a semiconductor device having a common output line connected to these connection lines, the selection signal is provided between the common source of the first and second N-type MOS transistor pairs of each differential amplifier circuit and the power supply. A semiconductor device, to which a fourth N-type MOS transistor having a gate input of a reverse phase selection signal is connected.