JPS6344399A - Write read circuit for semiconductor memory - Google Patents

Abstract

PURPOSE:To reduce an area that each circuit occupies and to attain high density and high integration by unifying the function of a driver circuit operating when data is written in a semiconductor memory and the function of a sense amplifier operating in a reading operation. CONSTITUTION:Channel P MOSFETs for the channel N MOSFET, TRT15 and TRT16 of transistors TRT13, TRT14, TRT17, TRT18 and TRT19 comprise the sense amplifier circuit and the driving circuit. A control signal phiR/-W becomes L or H according as a writing or reading action. The TRT13 and TRT14 to form a switch circuit are turned on and off. In writing data, write data from a data input signal D1 is inputted to an inverter circuit, and acts as a driver circuit. In reading data, data on a memory cell 1 becomes the potential difference between bit lines B and the inverse of B, and a control signal phiS' starts the action of a sense amplifier.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a data writing and reading circuit for a semiconductor memory.

2. Description of the Related Art FIG. 2 schematically shows a circuit for writing data into a memory cell of a semiconductor memory and a circuit for reading data from the memory cell. 1 is a memory cell, 2 is a latch/output Banoff 7 circuit, S2 is a sense amplifier circuit for reading data from the memory cell, D2 is a driver circuit for writing data to the memory cell, B, B
are a bit line pair, D and D are data lines for data input/output, WL Howard line +03 is a sense amplifier control signal, Y is a column address, and DW is a driver circuit control signal.

In the operation of reading data from the memory cell, the data held in the memory cell is transferred to the bit line B when WL rises.
H appears as a potential difference over time. When a potential difference sufficient for amplification by the sense amplifier is generated, the O8 signal starts sense amplifier amplification. Column address Y selected after being sufficiently amplified by the sense amplifier
The data is read out to the latch/output Banoff 7 circuit through the data line.

On the other hand, when writing data, the drive circuit operates in response to the control signal Ow to drive the data line, and the data is propagated onto the bit lines B and B of the selected column address. At this time, the sense amplifier circuit is in an operational 0FF (off) state, and data is written into the memory cell of the selected word line WL. In this way, the sense amplifier circuit in the operation of reading data from the memory cell and the data drive circuit in the operation of writing data to the memory cell are separated from each other via the data line.

Problems to be Solved by the Invention As described above, in the conventional example, the sense amplifier circuit and the driver circuit for writing are provided in different locations and the data lines are connected to each other, so that the wiring area and The area of each circuit portion occupies a large portion of the data output circuit portion, and is one of the factors that pose an obstacle in increasing the density and downsizing of semiconductor memories.

The present invention aims to reduce the area occupied by each circuit section by integrating a driver circuit section that operates when writing to a semiconductor memory and a sense amplifier circuit section that operates when reading a semiconductor memory, resulting in higher density and higher integration. This is to realize the following.

Means for Solving the Problems The present invention relates to the function of a driver circuit section of a write circuit when writing data to a memory cell in a semiconductor memory, and the function of a sense amplifier circuit which is an operating circuit when reading data from a memory cell. Both functions are realized by an integrated circuit configuration.

In other words, when writing data to a memory cell, it operates as a driver circuit consisting of an inverter circuit that propagates input data to a bit line, and when reading data from a memory cell, it operates as a data latch type sense amplifier circuit that latches the potential of the bit line. Configure a circuit that operates as

Effect of the Invention The present invention makes it possible to integrate an input data drive circuit for writing and a sense amplifier circuit for reading, which were conventionally configured separately, into a circuit configuration by using the means described above. It is possible to significantly reduce the area occupied by each circuit part, and also to reduce the area occupied by the wiring area. It will become even more effective. Further, as semiconductor memories become more dense and highly integrated, it is thought that reducing the area of the write driver circuit section and the read sense amplifier circuit section will become an even more important factor in the future.

Embodiment FIG. 1 shows a first embodiment of the present invention. In Figure 1, 1 is a memory cell, 2 is a latch/output buffer circuit, WL is a word line, B e]3 is a bit line pair, D and D are data lines, Y is a column address, and SD is a sense amplifier/sense amplifier/output buffer circuit. driver circuit.

aR/W is a control signal for the sense amplifier/driver circuit.

Das' is a control signal during sense amplifier operation and driver operation, and Dl is an input data signal. In the data read operation from the memory cell, data held in the memory cell is caused to appear on the bit lines B and B as a potential difference over time when the word line WL rises. At this time, the control signal OR/W of the sense amplifier/driver circuit is H at the time of reading.
” (high), transistors “131” and “14” constituting the bit line switch circuit are in the on state,
It is in a conductive state. At the timing when the data read from the memory cell becomes a potential difference between bit lines B and B, and the value becomes sufficient for the sense amplifier to operate without malfunction, the control signal O8'19 is turned on and the sense amplifier is activated. This operation has the same function as a latch type sense amplifier operation, and can rapidly amplify the potential difference appearing on the bit line.

The sufficiently amplified data is read out to the data line by the selected column address Y and transmitted to the latch/output buffer circuit.

On the other hand, when writing data to the memory cell, the control signal OR/W becomes "L" (low), so that the transistors "13' and 14, which constitute the switch circuit, are turned off, and T16, T1□ and T16+" The gate of 18 is in a non-conducting state with bit lines B and B, while the control signal O8'
Therefore, transistor T19 is in the on state, and T16 and T
1□ and data line D-D by "16" and "1B" respectively.
Viewed from the side, it constitutes an inverter circuit. Therefore, the write data sent from the data input signal D1 is input to the above-mentioned inverter circuit according to the selected column address Y. This inverter circuit operates as a write drive circuit, and bit line B
-WL selected by writing data to B
will be written to the memory cells of

In this way, the sense amplifier/driver circuit SD performs two functions: data amplification during data writing and data reading.
It can be seen that two separate functions can be realized by one circuit.

In addition, in the embodiment of FIG. 1, T131"141T1
□.

T18jT19 as N-channel MO3FET and T1
Although the sense amplifier/driver circuit for 61 ``1 f3 was constructed using a P-channel MO5FET, it is clear that the present invention can also be realized by a configuration using other transistors having the same function. If the same operation is possible for “H”
Either the value "" (high) or "L" (low) may be used to control the on-operation of the transistor.

Effects of the Invention As described above, according to the present invention, firstly, the sense amplifier circuit and the driver circuit can be realized in one circuit, thereby significantly reducing the area occupied by each within the semiconductor memory chip. Can be done. Second, the wiring area for data lines connected to the sense amplifier circuit and driver circuit can be omitted, making it possible to reduce the area thereof. Thirdly, the integrated circuit of the present invention can further simplify the data input/output circuit of a semiconductor memory, reducing the area of semiconductor memories with multi-bit input/output, and increasing the density and integration of semiconductor memories. It is very effective.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram showing one embodiment of the present invention, and FIG. 2 is a circuit diagram of a conventional example. SD...Sense amplifier/driver circuit, "R/
W...Write/read control signal, O12...
... Control signal during sense amplifier operation and driver operation, Dl ... Data input signal, T11 to T19 ...
...N and P channel MO9FET.

Claims (1)

[Claims] The input gate of the first inverter circuit is connected via a first switch circuit that can be electrically disconnected to one bit line, and the input gate of the first inverter circuit can be electrically disconnected to and from the other bit line of the bit line pair. An input gate of a second inverter circuit is connected via a second switch circuit, an output of the first inverter circuit is connected to the memory cell side of the second switch circuit on the other bit line, and The output of the second inverter circuit is connected to the memory cell side of the first switch circuit on the one bit line, and the data input/output line to the memory cell is connected to the first inverter circuit and the second inverter circuit. between the grounding electrode of the first and second inverter circuits and the ground potential, and between the first and second inverter circuits and the ground potential.
A write/read circuit for a semiconductor memory, in which at least one of a power supply electrode of a second inverter circuit and a power supply potential is connected via a switch circuit.