JPS6378395A - Write/readout circuit for semiconductor memory - Google Patents

Abstract

PURPOSE:To attain high density and high circuit integration by integrating a driver circuit section operated at the time of writing a semiconductor memory and a sense amplifier circuit section operated at the time of readout to reduce the area occupied by each circuit section. CONSTITUTION:In the readout of data from a memory cell, data stored in the memory cell appears as a potential difference on bit lines B, the inverse of B with time by the leading of a word line W1. A control signal phiR/the inverse of W, of a sense amplifier/driver circuit SD at an H at the time of readout, address selection is applied by a column address recorder Y, transistors (TRs) T11, T12 are turned on, and a potential difference appearing on the bit line is propagated to data lines D, the inverse of D. TRs T13, T14 are turned on by the phiR/the inverse of W, and data read on the bit line is propagated through the switch circuit and appears on input gates T15-T18 of the circuit acting as the sense amplifier circuit as a signal potential difference.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a data writing and reading circuit for a semiconductor memory.

2. Description of the Related Art FIG. 2 schematically shows a circuit for writing data into a memory cell of a semiconductor memory and a circuit for reading data from the memory cell. S2 is a sense amplifier circuit for reading data from memory cells, and column address Y
A data line B is connected to the data line D, which is a circuit that amplifies the data generated by the potential difference on the selected bit line B and B. D2 is a driver circuit for writing data into memory cell MC, WL is a word line, and φ
S is a sense amplifier control signal, φwH driver circuit control signal, and LloB is a latch/output cover sofa circuit.

In the data read operation from the memory cell, the data held in the memory cell is transferred to the bit line B by the rising edge of WL.
A potential difference appears on B over time. The potential difference selected by the column address Y and appearing on the nine pit line is propagated to the data line, and when a potential difference sufficient for starting amplification by the sense amplifier is generated on the data line, the sense amplifier control signal φS performs the sense amplifier operation. The sufficiently amplified data is then propagated to the latch/output Banoff 7 circuit and read out.

On the other hand, when writing data, the control signal φW causes the drive circuit to operate and the data line to drive the data to be selected by the control signal φW.
The signal on the data line is transmitted to the bit lines B and B. At this time, the sense amplifier circuit S2 is in the operating 0FF (off) state due to the signal φS, and the selected word line W
Data is written to the L memory cell. In this way, the drive circuit for writing data to the memory cell is configured and provided as a separate and independent circuit from the sense amplifier circuit for reading the data via the data line.

Problems to be Solved by the Invention As described above, in the conventional example, the sense amplifier circuit and the write driver circuit are provided in separate locations with independent circuit configurations, and the data lines are connected to each other.

For this reason, the area of these wiring areas and each circuit portion occupies a large portion of the data input/output section, leading to higher integration of semiconductor memories.

This is one factor that becomes an obstacle in downsizing.

The present invention aims to reduce the area occupied by each circuit section by integrating a driver circuit section that operates when writing to a semiconductor memory and a sense amplifier circuit section that operates when reading a semiconductor memory, resulting in higher density and higher integration. This is to realize the following.

Means for Solving the Problems The present invention relates to a function of a driver circuit section of a write circuit when writing data to a memory cell in a semiconductor memory, and a function of a sense amplifier circuit which is an operating circuit when reading data from a memory cell. Both functions are realized by an integrated circuit configuration.

In other words, when writing data to a memory cell, the inverter circuit is composed of an inverter circuit that propagates the input data to the bit line via the data line, and operates as a driver circuit, and when reading data from the memory cell, the potential difference that appears on the bit line and data line is generated. A circuit that operates as a latch-type sense amplifier circuit that amplifies the current is configured.

Effect of the Invention The present invention makes it possible to integrate the input data drive circuit for writing and the sense amplifier circuit for reading, which were conventionally configured separately, into an integrated circuit configuration by using the above-mentioned means. The area occupied by the wiring area can be significantly reduced, and the area occupied by the wiring area can also be reduced.

Reducing the wiring area of data lines is even more effective for semiconductor memories having multi-bit input/output bins. Mano, high density semiconductor memory.

As integration becomes higher, it is thought that reducing the area of the write driver circuit section and the read sense amplifier circuit section will become an even more important technology in the future.

Embodiment 1 FIG. 1': i is an equivalent circuit showing an embodiment of the cylinder 1 of the present invention. In Figure 1, MC is a memory cell, LloB is a latch/output panoramic circuit, WL is a word line, B and B are bit line pairs, D and D are data lines, Y is a column address, and S
D is a sense amplifier/driver circuit, φR/−1d is a control signal for the sense amplifier/driver circuit, φS is a control signal during sense amplifier operation and driver operation, and DI is an input data signal.

Data read operation from memory cells is performed using word line W1.
With the rising edge of , the data held in the memory cell appears on the bit lines B and B as a potential difference over time. At this time, the control signal φR/- of the sense amplifier/driver circuit is “H” (High) during reading.
Address selection is performed by column address recorder Y (transistors T11 and TI
2 is turned on and becomes a data line, and a potential difference appears on the bit line below and propagates to the data line. Transistor Tls, T・a Hao 7 (ON) due to the φRA signal mentioned above
The data read on the bit line propagates through this switch circuit and appears as a signal potential difference at the input gates Tl5, T16, T17, and T18 of the circuit that operates as a sense amplifier circuit, so that this sense amplifier circuit does not malfunction. At the timing when the value becomes sufficient to perform the operation, Tl is turned on by the control signal φS' and the sense amplifier operation is started. This operation is similar to that of a launch type sense amplifier, and is used for data and IJD.

It is possible to rapidly amplify the potential difference appearing at D. The sufficiently amplified data will be propagated to the latch/output sofa circuit via the input/output linework 0°IO.

On the other hand, when writing data to the memory cell, the control signal φR//- becomes If l,'' (Low), so that the transistors T+3+T+4 forming the reset circuit
is in the off state Tl5, Tl7, T16, T1
Since the gate of 8 and the data line D are in a non-conductive state, the control signal φS' causes the transistor Tl? Tl is set in the ON state during write operation.
5 and T17 and T16 and Tl8 form the input gates of the inverter circuit when viewed from the data input signal DI side. Therefore, the carefully written data sent from the data input signal Dr is inputted as data D and D, respectively, to the above-mentioned inverter circuit via the input/output lines IO and 10. This inverter circuit operates as a write drive circuit, and propagates through the data line and DK to bit lines B and B according to the selected column address Y.
The data is transmitted to and written into the memory cell of the selected word line WL.

In this way, it can be seen that the sense amplifier/driver circuit SD can realize two separate functions of voltage amplification of data during data writing and data reading with one circuit. In addition, in the embodiment shown in FIG. 1, +51
The sense amplifier/driver circuit was constructed using an N-channel MO3FET for T19 and a P-channel MO3FET for T15 + Tl6, but in the present invention, it can also be realized by a configuration using other transistors having the same function. is clear. Just in case, if the same operation is possible for another example of the control signal operation, "lH1 buy-・a)" or "L"
(Low) may be used to control the ON operation of the transistor, and there is no particular limitation.

Effects of the Invention As described above, according to the present invention, firstly, the sense amplifier circuit and the driver circuit can be realized in one circuit, thereby significantly reducing the area occupied by each within the semiconductor memory chip. can do. Second, the wiring area of the data line connecting the sense amplifier circuit and the driver circuit can be omitted, making it possible to reduce the area thereof. Thirdly, the integrated circuit of the present invention can further simplify the data input/output circuit of the semiconductor memory.
Reducing the area of semiconductor memory with multi-bit input/output.

This will be extremely effective in increasing the density and integration of semiconductor memories.

[Brief explanation of the drawing]

The first is a circuit diagram of a semiconductor memory according to an embodiment of the present invention, and FIG. 2 is a semiconductor memory circuit diagram of a conventional memory. SD...Sense amplifier/driver circuit, φ*/'7
...Write/read control signal, φ3...
... Control signal during sense amplifier operation and driver operation, DI ... Data input signal, T11 to T1p.
...N and P channel MO3FET, IO, IO
...Input/output line.

Claims (1)

[Claims] A first input/output line is connected to the first data line via a first switch circuit, a second input/output line is connected to the second data line via a second switch circuit, and the first input/output line is connected to the first data line via a second switch circuit. An input gate of a first inverter circuit is connected to the first input/output line, an output of the first inverter circuit is connected to the second data line, and a second inverter circuit is connected to the second input/output line. The input gate of the second inverter circuit is connected to the first data line, and the output of the second inverter circuit is connected to the first data line. A write/read circuit for a semiconductor memory, wherein at least one electrode between a power supply electrode of an inverter circuit and a VDD potential is connected via a switch circuit.