JPH04259987A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To suppress the increase of a chip size by limiting the amplitude of read information by an amplitude limit circuit in the case of a read operation and inputting a write data through the amplitude limit circuit and a transistor(TR) in the case of a write operation. CONSTITUTION:In the case of the read operation, an amplitude control signal phipassed through an OR circuit is turned to H, N channel TR Tr1 and Tr2 connected with a high potential power source VDD forming the amplitude limit circuit are turned on, and the amplitude of the data read out to a data bus DB and an anti-DB is limited. On the other hand, in the case of the write operation, N channel TR Tr9 and Tr10 connected with a low potential power source G form a write circuit together with the amplitude limit circuit, information is similarly written in the bus DB and the anti-DB, the configuration of an additional circuit for preventing an inside circuit malfunction caused by the power supply noise of an output circuit to output logic signals is simplified, and the increase of the chip size is suppressed.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to write and read circuits for semiconductor memory devices. In recent years, as the capacity of semiconductor memory devices has increased, the number of data buses has also increased, and with this, the number of circuits associated with each data bus has also increased. Therefore, since the chip area increases due to the increase in the number of auxiliary circuits, it is necessary to simplify the auxiliary circuits themselves to suppress the increase in the chip area.

0002

2. Description of the Related Art A data writing circuit for a data bus and an amplitude limiting circuit for a data bus in a conventional DRAM will be explained with reference to FIG. It is configured by connecting limiting N-channel MOS transistors Tr1 and Tr2, and the gates of the transistors Tr1 and Tr2 receive an amplitude limiting signal ΦD at H level during read operation.
is input, and based on the amplitude limit signal ΦD, the data buses DB and DBbar are connected to the transistor Tr from the power supply Vcc.
1 and Tr2 is maintained at a potential lowered by the threshold value Vth of Tr2, that is, at a potential that allows efficient operation of the current mirror circuit 4 connected to the data buses DB and DB bar.

Data writing circuits 1b and 1a are connected to data buses DB and DBbar, respectively. In the data write circuit 1a, N-channel MOS transistors Tr3 and Tr4 are connected in series between a write power supply such as a power supply Vcc and the ground G, and complementary write data WR and W are connected to the gates of the transistors Tr3 and Tr4.
R bar is input. In addition, in the data write circuit 1b, N-channel MOS transistors Tr5 and Tr6 are connected in series between a write power supply such as a power supply Vcc and the ground G, and complementary write data WR bar and WR are connected to the gates of the transistors Tr5 and Tr6. is input.

With such a configuration, in the standby state during the read operation, the transistors Tr1 and Tr2 are kept high.
The level amplitude limit signal ΦD is input to the data bus D.
B, DB bar is connected from power supply Vcc to transistor Tr1, T
The potential is maintained at a potential lowered by the threshold value Vth of r2, and in this state, the column selection gates Tr7 and Tr8 are opened by the column selection signal Φc at the H level, and the bit lines BL and BL are
When the bar is selected and the word line WL is selected, for example, memory cell 2 is selected, the cell information stored in the memory cell 2 is amplified by the sense amplifier 3 and transmitted via the bit lines BL and BL bar. The cell information is read out to the data buses DB and DB bar, and the cell information is further sent to the current mirror circuit 4.
is amplified and output. Therefore, data buses DB,D
The cell information read out to B-bar is transmitted through transistors Tr1,
Due to the operation of Tr2, the signal is efficiently amplified by the current mirror circuit 4 and output.

On the other hand, during a write operation, the amplitude limit signal Φ
D becomes L level and transistors Tr1 and Tr2 are turned off. In this state, for example, when write data WR at H level and write data WR bar at L level are input, transistor Tr3 of data write circuit 1a is turned on, and transistor Tr6 of data write circuit 1b is turned on. As a result, data bus DB becomes L level and DB bar becomes H level. Then, when the column selection gates Tr7 and Tr8 are opened and the bit lines BL and BL bar are selected, and the word line WL is selected and, for example, memory cell 2 is selected, the memory cell 2
Write data is written to via data buses DB, DB bar and bit lines BL, BL bar. Also, when the write data WR and WR bar are inverted, the data bus D
The write data input to B and DB bars is inverted,
The write data is written into the selected memory cell 2.

[0006]

[Problems to be Solved by the Invention] However, in the above configuration, one amplitude limiting transistor and one data writing circuit are required for each bit line, and as the capacity of the cell area increases, data As the number of buses DB and DB bars increases, the number of amplitude limiting circuits and data writing circuits also increases. Since the transistors constituting both circuits are required to be relatively large in size, there is a problem in that an increase in the number of both circuits immediately increases the chip size.

An object of the present invention is to provide a semiconductor memory device that can suppress an increase in chip size due to an increase in the number of data write circuits and amplitude limiting circuits connected to a data bus.

[0008]

[Means for Solving the Problems] FIG. 1 is a diagram illustrating the principle of the present invention. That is, an amplitude limiting circuit that limits the amplitude of cell information transmitted by a pair of data buses DB and DB bar during a read operation of cell information, and a data write circuit that inputs write data to the data buses DB and DB bar during a write operation. are connected to the data buses DB, DB bar, and the amplitude limiting circuit is connected to the pair of data buses DB, DB bar.
The data writing circuit is composed of a pair of transistors Tr1 and Tr2 connected between the DB bar and the high potential side power supply Vcc, and the data writing circuit is connected between the pair of data buses DB and DB bar and the low potential side power supply G. The amplitude limiting circuit includes a pair of transistors Tr9 and Tr10, and transistors Tr1 and Tr2 forming the amplitude limiting circuit.

[0009]

[Operation] During read operation, data bus DB,
The amplitude of the cell information read to DB bar is limited, and during a write operation, a data write circuit is constituted by the transistors Tr1 and Tr2 and transistors Tr9 and Tr10, and write data is input to data buses DB and DB bar.

0010

[Example] An example embodying this invention is shown below in Figure 2.
Explain according to the following. Incidentally, the same components as those of the conventional example are given the same reference numerals, and the explanation thereof will be omitted. In this embodiment, a cell array similar to that of the conventional example is connected to the data buses DB and DB bar, and N-channel MOS transistors Tr1 and Tr2 for amplitude limiting are connected to the power supply Vcc.
is connected. The gates of the transistors Tr1 and Tr2 are connected to the output terminals of the OR circuits 5a and 5b.
The amplitude limiting signal ΦD is input to one input terminal of the R circuits 5a, 5b, and write data WR, WR bar are input to the other input terminal.

Furthermore, between the data buses DB, DB bar and the ground G, there are N-channel MOS transistors Tr9,
Tr10 is connected, and write data WR and WR bar are input to its gate. Now, in the data writing circuit and amplitude limiting circuit configured in this way, during a read operation, the H level amplitude limiting signal ΦD is input to the OR circuits 5a and 5b, and the OR circuits 5a and 5b output an H level signal. Then, based on the output signal, transistors Tr1 and Tr2 are turned on, and an amplitude limiting operation of data buses DB and DB bar is performed during a cell information read operation.

On the other hand, when the read operation shifts to the write operation, the amplitude limit signal ΦD becomes L level as shown in FIG. In this state, for example, when H level write data WR and L level write data WR bar are input, the OR circuit 5a outputs an H level signal.
Since the OR circuit 5b outputs an L level signal, the transistor Tr1 is turned on and the transistor Tr2 is turned on.
is turned off. Furthermore, the transistor Tr9 is turned on and the transistor Tr10 is turned off. Therefore, data bus DB becomes H level, DB bar becomes L level, and the write data is written into the selected memory cell.

Furthermore, when the write data WR and WR bar are inverted, the write data input to the data buses DB and DB bar are inverted, and the write data is written into the selected memory cell. As described above, in this data write circuit and amplitude limiting circuit, during the read operation, the transistors Tr1 and Tr2 operate, and the data bus DB,
The amplitude of DB bar is limited, and write data is input to data buses DB and DB bar by transistors Tr1 and Tr2 and transistors Tr9 and Tr10 during a write operation. Therefore, by using transistors Tr1 and Tr2 in common for write and read operations, the number of transistors in the data write circuit and the amplitude limiting circuit can be reduced compared to the conventional example.
, DB, it is possible to suppress an increase in the area occupied by both circuits due to an increase in the number of DB bars, thereby preventing an increase in chip size.

Furthermore, compared to the conventional example, OR circuits 5a and 5b are newly required, but the size of the transistors constituting these OR circuits 5a and 5b is the same as that of the transistors constituting the data writing circuit and the amplitude limiting circuit. Since it is smaller than the size, reducing the number of transistors in the data writing circuit and the amplitude limiting circuit greatly contributes to reducing the chip area. Furthermore, although the data writing circuit and the amplitude limiting circuit must be placed near the data buses DB and DB bar, the OR circuits 5a and 5b are not necessarily connected to the data bus DB.
, DB bar, so reducing the number of transistors in the data writing circuit and the amplitude limiting circuit can also improve the degree of freedom in circuit layout.

[0015]

As described in detail above, the present invention has the advantage of being able to provide a semiconductor memory device that can suppress an increase in chip size due to an increase in the number of data writing circuits and amplitude limiting circuits connected to a data bus. It has a great effect.

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the principle of the present invention.

FIG. 2 is a circuit diagram showing an embodiment of the present invention.

FIG. 3 is a waveform diagram showing the operation of one embodiment.

FIG. 4 is a circuit diagram showing a conventional example.

[Explanation of symbols]

DB, DB bar Data bus WR, WR bar Write data Vcc High potential side power supply G Low potential side power supply Tr1, Tr2, Tr9, Tr10 Transistor ΦD Amplitude limit signal

Claims (1)

[Claims] 1. An amplitude limiting circuit that limits the amplitude of cell information transmitted on a pair of data buses (DB, DB bar) during a cell information read operation based on an input of an amplitude limit signal (ΦD), and a write operation. Sometimes a data bus (DB)
, DB bar) and a data write circuit that inputs write data (WR, WR bar) to the data bus (DB, DB bar).
Tr1, Tr2 is a semiconductor memory device connected to a high potential side power supply (Vcc), and the amplitude limiting circuit is a semiconductor memory device connected to a high potential side power supply (Vcc). ), and the data write circuit comprises a pair of transistors (Tr9, Tr10) connected between the pair of data buses (DB, DB bar) and the low potential side power supply (G), and the amplitude limiting circuit. 1. A semiconductor memory device comprising transistors (Tr1, Tr2).