JPS6022338A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To obtain a square shape and improve an integrity by a method wherein P-channel domains and N-channel domains are arranged alternately and common source lines and common ground lines are arranged in both channel domains in parallel and internal common lines are provided to the edges of the channel domains vertically. CONSTITUTION:P-channel domains 1 and N-channel domains 2 are arranged alternately and common source lines 3 and common ground lines 4 are provided to the domains 1 and the domains 2 respectively. Internal signal common lines 6 are provided to the edges of the domains 1, 2 and logic circuits A, B, E, F, C' and D' are formed between the domains 1 and the domains 2. The logic circuits, the signal lines and the common source lines are connected to each other properly. Because the internal signal common lines 6 are provided, signal common lines 5 need not be provided to the inside of the domains 1, 2 so that a square shape of the integrated circuit can be obtained and a high density integration can be realized.

Description

[Detailed Description of the Invention] [Technical field to which the invention pertains] The present invention relates to a semiconductor integrated circuit device, and in particular to a semiconductor integrated circuit device (0MO8).
I'd like to focus on a semiconductor integrated circuit device composed of transistors and capable of high-density integration.

[Prior art]

As is well known, a logic circuit using 0MO8) transistors consists of substantially the same number of P-channel MO8) transistors and N-channel MOS) transistors, and when implementing this into a semiconductor integrated circuit device, it is generally a P-channel MOS transistor. A region where a transistor is arranged (hereinafter referred to as a P-channel region) and a region where an N-channel transistor is arranged (hereinafter referred to as an N-channel region) are set close to each other in parallel, and the same number of MOs are placed in each region.
S) Arrange transistors to configure C individual logic circuits'C
There is.

FIG. 1 is an explanatory block diagram showing an example of a conventional semiconductor integrated circuit device, in which 1 is a P channel region, 2 is an N channel region, 3 is a power supply common line, 4 is a ground common line, and 5 is a signal The common lines, A-F, are individual logic circuits.

Logic circuits A to F each consist of CMOS transistors, with a P-channel transistor arranged inside a P-channel region 1 and an N-channel transistor arranged inside an N-channel region 2.

In FIG. 1, for the sake of simplicity, the connections between the logic circuits A and F and the connection between the signal common lines are omitted.

As can be seen from FIG. 1, the semiconductor multiplication circuit device having the configuration shown in FIG.
It's not always allowed.

FIG. 2 is an explanatory diagram showing a configuration in which the dimensions given to logic circuits A to F are close to square; in this case, a large number of power supply common lines 3, ground 4, and signal common lines 5 are used. As a result, an additional connection between the common terminals is required, which increases the area required for the entire C1.

[Purpose of the invention]

An object of the present invention is to eliminate the above-mentioned drawbacks (2) to provide a semiconductor integrated circuit device having a more dense layout configuration.

[Structure of the invention]

In the semiconductor integrated circuit device of the present invention, P-channel MO'8 transistor regions formed by arranging a plurality of transistors and N-channel MO8 transistor regions are alternately arranged in parallel, and these regions and other regions are connected to each other. In a semiconductor integrated circuit device having a first potential common line arranged near the center of the P-channel MOS transistor region excluding the end portions and the center of the P-channel MOS transistor region excluding the end portions, A second potential common line disposed near the end region and a first or first potential common line disposed near the outside of each region depending on whether it is a P channel MOS transistor region or a 1dN channel MO8 transistor region in the end region. 2, and connection wiring to other circuit blocks arranged outside the various common lines.

[Explanation of Examples]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 3 is a block diagram of an embodiment of the present invention.

In the figure, logic circuits A, B, E, and F are A in Figure 2.
, B, E, )', but the logic circuit C/, D' in FIG. 3 is the same as the logic circuit C, D' in FIG.
The arrangement of the P-channel transistors and the arrangement of the N-channel transistors in D are reversed. As a result, the P channel area 1. This can be done without reducing the number of N channel regions 2. Therefore, as can be easily understood by comparing FIG. 2 and FIG. 3, the power supply common line 3. The required number of ground common lines 4 is reduced from three to two. Reference numeral 6 denotes a signal common line for connecting each circuit within the block, and is called an internal signal common line to distinguish it from the signal common line 5. The internal signal common line 6 uses a layer different from the power supply common line 3 and the ground common line 4 to enable orthogonal lines.

In FIG. 3, connections between logic circuits, connections between logic circuits and internal signal common lines, and connections between internal signal common lines 6 and signal common lines 5 are omitted because they are easy. Since the arranged signal common lines are replaced, it becomes possible to eliminate the signal common lines inside the block, and it becomes possible to reduce the vertical area.

FIG. 4 is an explanatory diagram of another embodiment of the present invention, in which the power supply common line 3
There are three in total at both ends and in the center, and there are two ground common lines 4 in the center, indicating the case where the numbers of both common lines are not the same. 0' and H' are logic circuits.

As is clear from the figure, in the conventional system, four power supply common lines 3 and four ground common lines 4 were required, but in this embodiment, there are three power supply common lines, two ground common lines, and one each. and two 813 items decreased.

〔Effect of the invention〕

As explained above, according to the present invention, semiconductor integrated circuit devices can be arranged in a shape close to a square, and moreover,
The area occupied by common lines and the area lost for interconnection thereof can be reduced, and a semiconductor integrated circuit device with advanced density integration can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block explanatory diagram of an example of a semiconductor integrated circuit device according to a conventional configuration method, FIG. 2 is a block explanatory diagram of another example of a semiconductor integrated circuit device according to a conventional configuration method, and FIG.
The figure is a block explanatory diagram of one embodiment of the present invention, and FIG. 4 is a block explanatory diagram of another embodiment of the present invention. 1...P channel area, 2...N-
Channel area %3...Power supply common line, 4...
...Ground common line, 5...Signal common line, 6
...Internal signal common line. Agent: Patent Attorney Susumu Uchihara (:Pa,, 7H7◇) Atsushi 3
Figure z 4 closed

Claims (1)

[Claims] A circuit block in which P-channel MOS transistor regions and N-channel MOS transistor regions formed by arranging a plurality of transistors are arranged alternately in parallel, and wiring for connection within the circuit block and with external circuit blocks. In a semiconductor integrated circuit device having a first potential common line arranged near the center of the P-channel MOS transistor region excluding the ends, and a first potential common line arranged near the center of the P-channel MOS transistor region excluding the ends; -UP in the common line of the second potential and the end area
Channel MOS transistor region or N channel M
OS) A first or second potential common line placed near the outside of each transistor area, depending on the transistor area, and connection wiring to other circuit blocks placed outside the various common lines. A semiconductor integrated circuit device comprising: