JPH01129443A - Manufacture of semiconductor device having multilayer interconnection structure - Google Patents

Abstract

PURPOSE:To form two or more layers of multilayer interconnections extremely stably without generating defective insulation, disconnection, etc., by forming a trench in width slightly larger than a conductive-path forming predetermined region in an insulating film in a pattern through etching and shaping a conductive path into the trench while burying a clearance between the conductive path and the trench with silica and flattening the clearance. CONSTITUTION:A first insulating film 12 such as a thermal oxide film is formed onto the surface of a semiconductor substrate 11. A trench 13 in width slightly larger than the width of a first conductive path to be shaped in a postprocess is formed through etching by an etchant such as hydrofluoric acid. A metallic layer is shaped onto the whole surface and patterned, and the first conductive path 14 is formed into the trench 13. An SOG film 35 is applied onto the whole surface so as to bury a clearance between the side face of the trench 13 in the first insulating film 12 and the first conductive path 14. The SOG film 15 is etched back through ion etching by a gas such as CF4, the surfaces of the first conductive path 14 and the first insulating film 12 are exposed, SOG is left only in said clearances, and SOG regions 15a are formed. Accordingly, the first conductive path 14 is buried and shaped so that the surface of the conductive path 14 and the surface of the first in sulating film 12 are formed approximately flatly.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device having a multilayer wiring structure in which flat multilayer wiring is formed.

[Prior Art] FIG. 4 is a cross-sectional view showing a semiconductor device with a multilayer wiring structure manufactured by a conventional method. In this conventional method,
First, a first insulating film 2 is formed on a semiconductor substrate 1, and a metal film is formed on the first insulating film 2, and then patterned to form a first conductive path 3.Next, a nitride film or the like is formed on the entire surface. A second insulating film 4 is formed, and a silica (silicon oxide; hereinafter referred to as SOG) coating liquid is applied to a portion of the upper surface of the second insulating film 4 having a large step, thereby filling the step with an SOG region 5. Thereafter, the second conductive path 6 is patterned. In this prior art, disconnection of the upper wiring layer (second conductive path 6) is prevented by filling the step with the SOG region 5.

On the other hand, the prior art shown in FIG.
), a first insulating film 2 is formed on a semiconductor substrate l, a groove 7 whose side surfaces are inclined is formed in this first insulating film 2, and a metal film is patterned in this groove 7 to form a first insulating film 2. 1 conductive path 3 is formed. Then, a second insulating film 4 is formed on the entire surface,
A second conductive path 6 is patterned on this second insulating film 4. The side surface of this groove 7 is 15 to 45 mm with respect to the first insulating film 2.
The height of the portion where the first conductive path 3 protrudes upward from the upper surface of the first insulating film 2 is 3000 Å or less.

[Problems to be Solved by the Invention] However, in the prior art shown in FIG.
There is a problem that wiring becomes difficult. In particular, in the case of a bipolar integrated circuit, the thickness of the first conductive path 3 on the first insulating film 2 is about 1 μm. Therefore, in order to prevent wiring breakage in the second conductive path 6, the thickness of the second insulating film 4 is increased to 1 μm or more, and SOG, which is an insulator with relatively high viscosity, is applied to the portions where the difference is large. Although the SOG region 5 is filled by coating, there is a problem in that when there are three or more wiring layers, the unevenness becomes large and it becomes difficult to wire.

Furthermore, in the prior art shown in FIG. 5, the first conductive path 3
is formed in a groove 7 whose side surfaces are inclined at a taper angle of 15 to 45 degrees, and is covered with a second insulating film 4. There is a problem in that a depression occurs, which may deteriorate the step coverage of the second conductive path 6.

The present invention has been made in view of such problems, and includes:
It is an object of the present invention to provide a method for manufacturing a semiconductor device having a multilayer wiring structure, which can avoid the risk of insulation failure and disconnection, and can provide flat multilayer wiring.

[Means for Solving the Problems] A method for manufacturing a semiconductor device with a multilayer wiring structure according to the present invention includes:
a step 9 of forming an insulating film on the semiconductor substrate 1 on which the semiconductor element is formed; a step of etching away the insulating film in a predetermined pattern while leaving a portion of the insulating film in the thickness direction to form a groove; a step of depositing a metal layer inside the groove to form a conductive path; a step of depositing a silica coating film while filling the gap between the side surface of the groove and the side surface of the conductive path; and a step of depositing the silica coating film. The method is characterized by comprising a step of etching back to expose the surface of the conductive path.

[Function] In the present invention, a groove slightly wider than the width of the conductive path to be formed is formed in the insulating film on the semiconductor substrate, and after forming the conductive path in this groove, the conductive path and the side surface of the groove are Fill the space completely with silica coating. Then, this silica coating film is etched back to expose the surface of the conductive path. As a result, the conductive path can be embedded in the insulating film, and the surface of the conductive path and the surface of the insulating film are approximately flush with each other.
If the second insulating film is formed over the entire surface after the etch-back process, a flat insulating film without depressions can be formed. Therefore, if the second conductive path is formed on the second insulating film, no insulation failure will occur in the second insulating film, and no disconnection will occur in the second conductive path.

[Example] Next, an example of the present invention will be described with reference to the accompanying drawings.

FIGS. 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device with a multilayer wiring structure according to an embodiment of the present invention in order of steps;
FIG. 2(a) shows this embodiment method 12. - A cross-sectional view showing a multilayer wiring structure formed from the above, and the second figure (b) is a plan view thereof.

First, as shown in FIG. 1(a), a first insulating film 12 such as a thermal oxide film is formed on the surface of a semiconductor substrate 11. Next, a groove 13 having a width slightly larger than the width of the first conductive path to be formed in a later step is formed by etching with an etching liquid such as hydrochloric acid. The depth of this groove 13 is approximately the same as the thickness of the metal layer constituting the first conductive path, and is approximately 1 μm (1 μm) to the extent that the first conductive path is buried. MO3
The first insulating film 12 is left with a thickness that does not produce any effect (500 Å or more).

Next, as shown in FIG. 1(b), a metal layer is formed on the entire surface and then patterned to form a conductive path 14 in the groove 13. Since the width of the first conductive path 14 is slightly narrower than the width of the groove 13, there is a gap between the side surface of the second groove 13 and the first conductive path 14. Therefore, the 80G film 15 is applied to the entire surface so as to fill this gap.

1-J<, as shown in FIG. 1(c), the SOG film 1
-! 5 is etched back by ion etching using a gas such as CF4 to form the first conductive path 14 and the first insulating film 12.
The SOG region 15a is provided by exposing the surface of and leaving SOc= only in the gap.

1.1 From this, the first conductive path 14 is connected to its surface and the first conductive path 14.
It can be formed by being embedded in the first insulating film 12 so that the surface thereof is substantially flush with the surface of the insulating film 12.

After that, a second insulating film is formed by depositing a nitride film or the like to a thickness of about 1 μm by plasma CVD. 6 is formed on the entire surface.

Next, a second conductive path 17 orthogonal to the first conductive path 14 is laid on the second insulating film 16 .

The first insulating film 12 and the first insulating film 12 formed in the manner
The "I" electric path 14 has a small level difference on its surface and a high pitch. Therefore, the second insulating film 6 formed between the first conductive path 14 and the second conductive path 17 has extremely high flatness and has no stepped portion, thereby avoiding insulation defects. Moreover, the second conductive path 17 on the second insulating film 16 is not disconnected. In this way, a multilayer wiring having two or more layers can be stably formed.

FIG. 3 is a sectional view showing a semiconductor device having a multilayer wiring structure manufactured by the second embodiment method of the present invention. In this embodiment, as in the first embodiment, the first insulation wA1
2 is not formed by a single layer of thermal oxide film, but first the lower insulating film 18 is formed by thermal oxidation, and then an oxide film is formed on this lower insulating film 18 by atmospheric pressure CVD. By forming the upper insulating film 19 by burying the
It has a layered structure. Then, the upper insulating film 19 or the lower and upper insulating films 18 and 19 are selectively etched to form the groove 13 with at least a portion of the lower insulating film 18 remaining. Thereafter, a first conductive path 14 is formed in this groove 13.

Next, the gap 4 S between the first conductive path 14 and the side surface of the groove 13 is
The entire surface is covered with an SOG film so as to be filled with OG, and the SOG film is etched back to remove the 60G film on the surface of the 14th electric circuit 14 and the surface of one of the upper insulating layers, and the SOG film is deposited in the gap. Region 15a is left. Then,
A second insulating film 16 and a second conductive path 17 are formed in the same manner as in the first embodiment.

Also in this embodiment, since the surface of the first conductive path 4 and the surface of one of the upper insulating films of the first insulating film 12 are flat and substantially flush with the ζ plane, the same effect as in the first embodiment is achieved. . Also,
In this embodiment, since the first insulating film 12 has a two-layer structure of a lower layer and an upper layer insulating film 18, 19, the insulating film 18 formed by thermal oxidation of the lower layer can be thin. For this reason,
There is an advantage that the thermal oxidation time is short in the element formation stage.

[Effects of the Invention] 11 As explained above, according to the present invention, a pattern is formed in the insulating film by etching to form a groove having a width slightly larger than the area in which a conductive path is to be formed, and a conductive path is formed in this groove. At the same time, since the gap between the conductive path and the groove is filled with silica and flattened, wiring defects such as poor insulation and disconnection can be avoided when another insulating film and conductive path are formed on this conductive path. can do. Therefore, according to the present invention, a multilayer wiring having two or more layers can be formed extremely stably and without causing insulation defects, disconnections, etc., and has great effects in manufacturing semiconductor devices.

[Brief explanation of the drawing]

FIGS. 1(a) to <c> are cross-sectional views showing a method for manufacturing a semiconductor device with a multilayer wiring structure according to an embodiment of the present invention in order of steps;
FIG. 2(a) is a cross-sectional view showing a multilayer wiring structure formed by the method of this embodiment, FIG. 2(b) is a plan view thereof, and FIG. 3 is a multilayer wiring structure formed by the method of the second embodiment. 4 and 5 are cross-sectional views showing a semiconductor device with a multilayer wiring structure manufactured by a conventional method.

Claims (2)

[Claims] (1) A step of forming an insulating film on a semiconductor substrate on which a semiconductor element is formed, and a step of etching away this insulating film in a predetermined pattern while leaving a part of the insulating film in the thickness direction to form a groove. , a step of depositing a metal layer inside the groove to form a conductive path, a step of depositing a silica coating film while filling the gap between the side surface of the groove and the side surface of the conductive path, and the silica coating. A method for manufacturing a semiconductor device with a multilayer wiring structure, comprising the step of etching back a film to expose the surface of the conductive path. (2) The insulating film has a two-layer structure, and in the step of forming the groove, at least the upper insulating film is etched and removed in a predetermined pattern, and at least a part of the lower insulating film remains. A method of manufacturing a semiconductor device with a multilayer wiring structure according to claim 1, characterized in that a groove is formed.