JPH01125555U - - Google Patents
Info
- Publication number
- JPH01125555U JPH01125555U JP2047088U JP2047088U JPH01125555U JP H01125555 U JPH01125555 U JP H01125555U JP 2047088 U JP2047088 U JP 2047088U JP 2047088 U JP2047088 U JP 2047088U JP H01125555 U JPH01125555 U JP H01125555U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- wiring board
- chip mounting
- metal foil
- device characterized
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 claims description 5
- 239000011888 foil Substances 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims description 2
- 230000001681 protective effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
Description
第１図は本考案による一実施例を示す断面図、
第２図は従来の実装構造を示す断面図である。
１：プリント基板、２：配線、３：保護膜、４
：半導体チツプ、８：裏面金属箔。
FIG. 1 is a sectional view showing an embodiment of the present invention;
FIG. 2 is a sectional view showing a conventional mounting structure. 1: Printed circuit board, 2: Wiring, 3: Protective film, 4
: Semiconductor chip, 8: Back metal foil.
Claims (1)
あつて、半導体チツプ搭載部を充分に覆つて密着
された金属箔とからなることを特徴とする半導体
装置の実装構造。[Scope of Claim for Utility Model Registration] Consisting of a wiring board on which a semiconductor chip is mounted, and a metal foil that is tightly adhered to the wiring board surface opposite to the semiconductor chip mounting surface, sufficiently covering the semiconductor chip mounting area. A mounting structure for a semiconductor device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988020470U JP2554059Y2 (en) | 1988-02-18 | 1988-02-18 | Semiconductor device mounting structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988020470U JP2554059Y2 (en) | 1988-02-18 | 1988-02-18 | Semiconductor device mounting structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01125555U true JPH01125555U (en) | 1989-08-28 |
| JP2554059Y2 JP2554059Y2 (en) | 1997-11-12 |
Family
ID=31236865
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988020470U Expired - Lifetime JP2554059Y2 (en) | 1988-02-18 | 1988-02-18 | Semiconductor device mounting structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2554059Y2 (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59132641U (en) * | 1983-02-25 | 1984-09-05 | 日本電気株式会社 | Substrate for semiconductor devices |
| JPS60154543A (en) * | 1984-01-24 | 1985-08-14 | Nec Corp | Semiconductor device using synthetic resin substrate |
| JPS62235799A (en) * | 1986-04-07 | 1987-10-15 | 日本電気株式会社 | Hybrid integrated circuit device |
-
1988
- 1988-02-18 JP JP1988020470U patent/JP2554059Y2/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59132641U (en) * | 1983-02-25 | 1984-09-05 | 日本電気株式会社 | Substrate for semiconductor devices |
| JPS60154543A (en) * | 1984-01-24 | 1985-08-14 | Nec Corp | Semiconductor device using synthetic resin substrate |
| JPS62235799A (en) * | 1986-04-07 | 1987-10-15 | 日本電気株式会社 | Hybrid integrated circuit device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2554059Y2 (en) | 1997-11-12 |