JPH01123359U - - Google Patents

Info

Publication number
JPH01123359U
JPH01123359U JP1988020150U JP2015088U JPH01123359U JP H01123359 U JPH01123359 U JP H01123359U JP 1988020150 U JP1988020150 U JP 1988020150U JP 2015088 U JP2015088 U JP 2015088U JP H01123359 U JPH01123359 U JP H01123359U
Authority
JP
Japan
Prior art keywords
circuit device
fixed
device chip
circumference
lead frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1988020150U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1988020150U priority Critical patent/JPH01123359U/ja
Publication of JPH01123359U publication Critical patent/JPH01123359U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05554Shape in top view being square

Landscapes

  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【図面の簡単な説明】
第1図は一実施例を示す平面図、第2図A、同
図Bは同実施例におけるワイヤボンデイング動作
を示す平面図、第3図及び第4図はそれぞれ従来
のパツケージを示す平面図である。 3……ICチツプ、4……パツド、11……パ
ツケージ、12……リードフレーム。

Claims (1)

    【実用新案登録請求の範囲】
  1. リードフレームのボンデイング位置が円周上に
    、かつ、等間隔に配置されており、前記円周の円
    の内側に半導体集積回路装置チツプが固定される
    領域が設けられており、固定された半導体集積回
    路装置チツプのパツドと前記リードフレームのボ
    ンデイング位置の間にワイヤボンデイングが施こ
    されるパツケージ。
JP1988020150U 1988-02-17 1988-02-17 Pending JPH01123359U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1988020150U JPH01123359U (ja) 1988-02-17 1988-02-17

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1988020150U JPH01123359U (ja) 1988-02-17 1988-02-17

Publications (1)

Publication Number Publication Date
JPH01123359U true JPH01123359U (ja) 1989-08-22

Family

ID=31236276

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1988020150U Pending JPH01123359U (ja) 1988-02-17 1988-02-17

Country Status (1)

Country Link
JP (1) JPH01123359U (ja)

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