JPH01122634U

JPH01122634U -

Info

Publication number: JPH01122634U
Application number: JP1753188U
Authority: JP
Priority date: 1988-02-15
Filing date: 1988-02-15
Publication date: 1989-08-21

Description

[Brief explanation of the drawing]

第１図はこの考案の一実施例を示すブロツク図
、第２図は第１図の各部の信号波形を示す波形図
、第３図は第１図のスイツチ回路の接続を示す接
続図、第４図は従来のスイツチ回路を示す接続図
。１……発振器、２１，２２，２３……それぞれ
Ｆ／Ｆ、３０，３１，３２，３３……それぞれ出
力信号、４０，４１，４２，４３……それぞれス
イツチ回路、５……出力信号線、６……デコーダ
、Ｔｒ１，Ｔｒ２……ロード回路を構成するｐチ
ヤネルのスイツチング・トランジスタ、Ｔｒ３，
Ｔｒ４……ドライバ回路を構成するｎチヤネルの
スイツチング・トランジスタ。なお、図中同一符
号は同一または相当部分を示す。 Fig. 1 is a block diagram showing an embodiment of this invention, Fig. 2 is a waveform diagram showing signal waveforms of each part in Fig. 1, Fig. 3 is a connection diagram showing the connection of the switch circuit in Fig. 1, Figure 4 is a connection diagram showing a conventional switch circuit. 1: Oscillator, 21, 22, 23: F/F, 30, 31, 32, 33: Output signal, 40, 41, 42, 43: Switch circuit, 5: Output signal line, 6... Decoder, Tr1, Tr2... P channel switching transistor constituting the load circuit, Tr3,
Tr4...N-channel switching transistor that constitutes the driver circuit. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims

[Claims for Utility Model Registration] An oscillator that generates the highest clock frequency within a desired range of clock frequencies, and a T-type flip-flop that divides the output frequency of this oscillator into 1/2 for each stage are connected in N stages. A frequency divider circuit is provided corresponding to the output signal of the oscillator and the output signal of each stage of the frequency divider circuit, and the corresponding output signals are inputted to switch elements constituted by clocked inverters. A decoder that controls each switch circuit and enables output from only one selected switch circuit among all the switch circuits, and outputs the logical sum of the outputs of all switch circuits. In a clock frequency selection device having a common output signal line, each of the above-mentioned switch circuits has two p-channel switching transistors connected in series, one end of which is connected to the positive terminal of the power supply, and the other end to the signal output terminal. and a driver circuit configured by connecting two n-channel switching transistors in series, one end of which is connected to the signal output terminal and the other end to the negative terminal of the power supply. is applied to the gate of a p-channel switching transistor connected to the positive terminal of the power supply and to the gate of an n-channel switching transistor connected to the negative terminal of the power supply, and the control signal from said decoder is applied to said signal output terminal. A control signal applied to the gate of the p-channel switching transistor connected to the switching transistor and the gate of the n-channel switching transistor connected to the signal output terminal, and input from the decoder to each switch circuit, When the same input signal as the input signal input to the circuit is input as a reset signal to the input T-type flip-flop and the output from the switch circuit is controlled to pass, the corresponding T-type flip-flop is kept in the reset state. A clock frequency selection device characterized by controlling as follows.