JPS63109608A - Variable speed type up-down counter - Google Patents

Abstract

PURPOSE:To improve the operability by comparing and judging a pushing time of a hand push switch with a setting time of plural timers whose setting time is longer sequentially and using a selector so as to select an output clock of a clock generator and its frequency divider thereby quickening the count speed and reducing the measuring time. CONSTITUTION:Two hand-push switches 4-1, 4-2 starting the up/down count of a variable speed type up-down counter 3, a timer 5 outputting a logic signal when a pushing time of either of the switches 4-1, 4-2 exceeds plural setting times T1, T2, Tn whose time length is longer sequentially, and a selector 6 using a logic signal outputted from the timer 5 to select the output clock of the clock generator 1 and the frequency divider 2, are provided. Moreover, the count speed is varied automatically depending on the length of the pushing time of the switches 4-1, 4-2. Since the counter whose count speed is accelerated sequentially depending on the hand-switch pressing time of the count start is constituted, the operability is improved remarkably.

Description

[Detailed Description of the Invention] [Summary] The press time T of the hand switch that starts the counting operation of the up/down counter is compared with the set times of a plurality of timers that increase in length, and a selector is used to control the clock generator and By selecting the output clock of the frequency divider, the counting speed of the counter is accelerated and the measurement time is shortened as the hand-pressing time T becomes longer.This variable speed up/down counter has good operability.

[Industrial application field]

The present invention relates to a count amplifier and an up/down counter that counts down, and particularly to an up/down counter with variable counting speed.

Up/down counters have built-in processors and are used in various measurement fields such as intelligent measuring instruments, but they usually perform counting operations that count up or down at a constant counting speed.

There are two possible measurement modes: automatic measurement and manual measurement, but the manual measurement mode in particular requires a lot of manual work such as presetting operations.

When considering these man-machine interfaces,
The easy-to-use up/down counter is a major prize in terms of ease of use of measuring equipment.

As an up/down counter, it requires little manual operation.
It is desired that the counting speed be automatically varied and the time required for manual measurements to be significantly reduced.

[Prior Art] The configuration of a conventional variable speed up/down counter is shown in the block diagram of FIG.

Number l is a clock generator, 2-1. 2-2 is a frequency divider with an arbitrary frequency division ratio N, M, 3-1.3-2
is an up/down counter, 4-1, 4-2 is a hand switch, and 6^ is a changeover switch.

The clock generated by the clock generator 1 is frequency-divided by a frequency divider 2-1, 2-2 with an appropriate frequency division ratio N, M, and two types of clock pulse signals S with different periods are generated.
t, obtain S2.

Two types of clock signals S1 with different periods. S2 is selected by the changeover switch 6A, and the counters 3-1 and 3-
It is input to the CLK terminal of 2 to switch the counting clock, but
The counting clock of the counter 3-1, 3-2 is changed to 1/N of the clock number of the original clock generator 1, or 17M.

Further, to switch between up counting and down counting, the hand switch 4-1 can be pressed to perform up counting, and the switch 4-2 can be pressed to perform down counting.

In the conventional example shown in FIG. 4, only two types of measurement speeds can be selected.
A desired measurement speed can be obtained by increasing the number of stages 2-2 and switching the clock signal from the middle using a changeover switch.

[Problem that the invention seeks to solve]

As mentioned above, the conventional variable speed up/down counter can obtain a desired measurement speed by switching the period of the clock pulse, but when switching the measurement speed, the fourth
In the example shown in the figure, it is necessary to operate switches at two locations, and there is also the problem that increasing the number of stages of the frequency divider and performing manual switching between multiple stages is cumbersome in terms of operation.

[Means for solving problems]

The above problems are solved by the present invention, which automatically speeds up the counting operation of the counter by holding down the hand switch 4-1.4-2 that starts up-counting and down-counting. Ru.

Therefore, as shown in the principle block diagram in Figure 1, there is a clock generator 1 that generates a clock signal, a frequency divider 2 that divides the output, and the output clocks of the clock generator 1 and frequency divider 2 are used as a counting clock. In addition to the up/down counter 3 that inputs input and starts up/down operation with hand switches 4-1 and 4-2, the time T during which either hand switch 4-1 or 4-2 is pressed is , a plurality of set times T 1 of increasing length in order
．． T2. When Tn is exceeded, a timer circuit 5 outputs a logic signal each time, and the logic output of the timer circuit 5 is inputted as a selection signal, and the clock generator 1,
A selector 6 is provided for selectively outputting each output clock of the frequency divider 2.

[Function] The timer circuit 5 determines that the time T during which the up hand switch 4-1 or the down switch 4-2 is pressed is a set time T1. T2. Tn (TI<72
<Tn), it performs a judgment operation and outputs a logic signal.

The selector 6 inputs the logic output of the timer circuit 5 as a selection signal, and selects and outputs each output clock pulse from the clock generator 1 and frequency divider 2.

The frequency of the clock pulse selectively output from the selector 6 decreases in the order of the output of the clock generator 1 and the frequency divider 2. Naturally, the pulse period becomes longer in the order of the above outputs.

The up/down counter 3 inputs the clock pulses from the selector 6 to the CLK terminal to vary the counting speed of the up/down counter 3.

Therefore, as the up/down counter 3, simply by holding down the hand switch 4-1 or 4-2, the measurement speed changes from low to high speed, which shortens the time required for measurement, improves operability, and solves the problem. be done.

〔Example〕

FIG. 2 shows a block configuration of a variable speed up/down counter according to a first embodiment of the present invention.

The timers 5-1.5-2.5-n in FIG. 2 correspond to the timer circuit 5 in the principle block diagram of FIG. 1, and the channel selector corresponds to the selector 6. In addition, the up/down selector 7 is the count up (UP) switch 4-
1. SWl and countdown (DOWN) switch 4
-2. This is a logical OR circuit that selects any one signal (ground signal) of SW2, and is provided for practical convenience.

The other circuits in FIG. 2 are the same as the circuits in the principle block diagram of FIG. 1, and the same numbers and symbols have the same functions.

Now, when the hand switch SWI (for UP) is pressed, the up/down counters 3-1.3-2.3-n start counting up. At the same time, the SWI ground signal is input to the timer circuit 5 via the up/down selector 7.

In the timer circuit 5, the time T during which the switch SWI is pressed is
When T becomes longer than the set value T1, the timer 5-1 operates first and outputs a logic level 1, and then the time T becomes longer than the set value T2.
When the timer 5-2 becomes longer than Tn (Tl<T2<Tn), the timer 5-2 and then 5-n operate, each outputting a logic level 1.

The logic output of the timer 5-1.5-2.5-n is input as a selection signal to the input terminals ^, B, and N of the channel selector 6 to perform a selector operation.

The channel selector 6 also has an input terminal C01CL.
C2+Cn, frequency divider 2-n, 2-2.2, respectively
-1° Each output clock of the clock generator l is input, but the frequency of the clock pulse is high, medium, high, The pulse repetition period length increases in the order of the above outputs.

The channel selector 6 selects each of the above-mentioned clock pulse signals based on the selection signals inputted to the input terminals A, B, and N, and outputs the selected clock pulse signals to the up/down counter 3.

To summarize, if the time T for which the wife #cheating member is pressing a certain switch 1 or SW2 is T<TI, selector 6 is 00.
If manual power is selected and the measurement speed is low, T2) If T>T1, selector 6 selects 61 manual power and the measurement speed is medium speed, T2).
>Tn, the selector 6 selects the Cn input and outputs a lock pulse from the output terminal Y so that the measurement speed becomes high.

These clock pulses output from the output terminal Y of the selector 6 are supplied to the CLK terminals of the counters 3-1.3-2.3-n to perform counting operations.

The up/down counter 3-1.3-2.3-n performs a counter operation in which the longer the hand-pressing time T becomes, the faster the measurement speed becomes.

Further, when the hand switch SWI is released, the counter operation is immediately stopped and the counter returns to the initial state.

Although the up/down counter of this embodiment performs a counter operation in which one cycle is extremely long, the counting speed can be varied sequentially by key operation of one hand switch, thereby increasing operability and shortening the counting time.

Although the above description has been made regarding the count amplifier operation, completely similar operations can be performed for the countdown operation.

FIG. 3 is a block diagram of a variable speed up/down counter according to a second embodiment of the present invention, in which the frequency divider 2-1, 2-2 part and the selector 6 part of the first embodiment are shown. is replaced by a programmable frequency divider that can directly obtain an arbitrary frequency division ratio by programming, and similarly realizes the idea of the present invention.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to configure a counter whose counting speed is sequentially accelerated depending on the time when the hand switch for starting counting is pressed, thereby providing a man-machine interface with good operability.

[Brief explanation of the drawing]

FIG. 1 is a principle block diagram showing the configuration of a variable speed 7-sub/down counter according to the present invention. FIG. 2 is a block diagram of a variable speed up/down counter according to the first embodiment of the present invention. FIG. FIG. 4 is a block diagram of a variable speed up/down counter according to a second embodiment of the present invention, and FIG. 4 is a block diagram of a conventional variable speed up/down counter. In the first, second, third and fourth figures, 1 is a clock generator, 2 is a frequency divider, 3 is an up/down counter, 4-1.4-2 is a hand switch, 5 is a timer circuit, 6 is a It is a selector. wood,! 7F: Lo piece n induced concatenation a 11. 7O-J7fJ7' 2 table threat/lai'Jf 1 bulge>A... Figure 2 Lie Counter Figure 4

Claims (1)

[Claims] [1] Selecting the output of a clock generator (1) that generates a clock signal and the output clock of a frequency divider (2) that divides the output of the clock generator (1). In the variable speed up/down counter (3) that performs up and down counting operations by varying the measurement speed, two hand-press switches ( 4-1, 4-2) and the hand switch (4
-1, 4-2) Multiple set times (T1, T2, Tn) in which the length of time that either one of them is pressed becomes longer in sequence
a timer (5) that outputs a logic signal when the timer (5) exceeds the frequency of , a variable speed up/down counter characterized in that the counting speed is automatically varied depending on the length of time for which the hand switches (4-1, 4-2) are pressed. [2] The frequency divider (2) and the selector (6) are comprised of a programmable frequency divider whose frequency is directly divided by a program, and the programmable frequency divider is driven by the output of the timer (5). A variable speed up/down counter according to claim 1, wherein the counting speed is variable.