SU1403325A1 - Device for controlling two-phase electric motor - Google Patents

Abstract

The invention relates to electrical engineering and can be used in digital automatic control systems for two-phase asynchronous electric motors. The aim of the invention is to simplify. When introduced to a device for controlling a two-phase electric motor, which contains a master oscillator 1, a controlled frequency divider 2, a counter 3, a decipher 4, elements AND 5.6, RS-triggers 7,8,9,10, switch 13 and key amplifiers 14,15, elements ZILI 11 and 4ILI 12, connected respectively, with the first outputs of the decoder 4 and the input of the element I 5 and with the outputs of the RS flip-flops 7,8,9,10 and the input of the installation in O of the counter 3, provide the required accuracy and discreteness adjusting the rotational speed and torque of the electric motor with sufficient simplicity p alizatsii device. 2 Il. with S (L with

Description

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with y

ate

The invention relates to electrical engineering and can be used in digital automatic control systems for two-phase asynchronous electric motors.

The aim of the invention is to simplify.

FIG. 1 shows a block diagram of the deviceJ in FIG. 2 - time diagrams that show his work.

The device for controlling a two-phase electric motor (Fig. T) contains a master oscillator 1, a controlled frequency divider 2, a sequence But connected counter 3 and a decoder 4, two elements 5 and 6, four RS-flip-flops 7-10, element ZILI 11, element 4ILI 12, switch 13, the first and second key amplifiers Yai 14 and 15. The output of the master oscillator 1 is connected to the inputs of counter 3 and a controlled frequency divider 2, the input of which is connected to the first rohod of the first element 5, the second input of which is connected to output element ZILI 11, the inputs of which are connected same with the first, second and third outputs of the decoder 4, the S input of the first ks-flip-flop 7 is connected to the output of the first And 5 element, the R-input of the first CB-flip-flop 7 is combined with the S-input of the second.RS-flip-flop 8 and connected to b that output of the decoder 4, the R-input of the Second RS-flip-flop 8 is connected to the tiepBOMy output of the decoder 4, the outputs of the first and Boi Oporo RS-flip-flops 7 and 8 are connected to the inputs of the first key amplifier 14, the outputs of which are intended to be connected to the main motor of an electric motor 16. SB-KQK of the third RS-flip-flop 9 with the release of the second element And 6, the first input of which is combined with the R-input of the fourth RS flip-flop 10 And is connected to the fourth output of the decoder 4, the Second input of the second element And 6 is connected to the output of the first RS-TpHrreipa 7. The R-input of the third and B-input. the fourth RS-trIGGers 9–10 are combined and connected to the sixth output of the decoder 4. Outputs. The third and fourth RS-flip-flops 9 and 10 through the switch 13 are connected by a second key amplifier 15, the outputs of which are intended to be connected to the control winding of the electric motor. 16, the inputs of the element 4ШШ 12 are connected to the outputs corresponding to

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P

j 0 5

0

five

0

five

TO

RS-flip-flops 7-10, and the output of the element 4IL 12 is connected to the input of the installation in zero of the counter 3.

The controlled frequency divider 2 is conveniently performed as a series-connected divider 17 with a variable division factor and an unmanaged divider 18,

The device works with Ledunltsim way.

The master oscillator 1 indicates the square-wave pulses (Fig. 2a), the frequency of which is equal to

f - If. m f i-jr maize & )

where K NMOKO division ratio

controlled divider 2 frequency;

division factor of the frequency divider 18; maximum value

variable coefficient-. dividing divider 17

frequencies}

fgg is the operating frequency of the asynchronous motor,

. These pulses are sent to the counting inputs of the counter 3 and the controlled frequency divider 2, the division factor of which is determined by the value of the control code 19,

In the initial state, the first, second, third, and fourth RS-flip-flops 7–10 are in the zero state and, from their direct outputs, logic O signals are simultaneously present at the inputs; logic element 4IL or 12, whose output signal holds down the input to the O device counter 3 6 zero state. This leads to the appearance at the first output (output - 0) of the decoder 4 of a logic signal M (FIG. 2g), which, when coinciding with the output signal of frequency divider 2 (FIG. 2b), sets the first RS flip-flop 7 to the state logical 1 at the output (fig 2z), at the same time, on the code of element 4Ш1И 12 a signal is generated logical 1, taken from counter 3 a ban on counting input pulses from the master oscillator 1 (fig 2a), at a count of three, on the fourth (pin 3) Output of the decoder 4 (FIG. 1), the signal of logical 1 is received (FIG. 2e), which, when coincided at the input of the Ytoroy element I 6 with a logical 1 direct output signal

The first RS flip-flop 7 sets the third RS flip-flop 9 to the state of logical 1 .. at the output (Fig. 2i).

With a count of six, the fifth output (pin 6) of the decoder 4 generates a logical 1 signal (Fig. 2e), which sets the first RS flip-flop 7 to the logical O state, and the second RS flip-flop 8 is logical 1 (Fig. 2h, k).

When the count is equal to nine, the sixth output (pin 9) of the decoder 4 has a standard logical signal 1 (Fig. 2g), which sets the third RS flip-flop 9 to the logical O state, and the fourth RS flip-flop to the logical 1 (Fig. 2i, l).

After the counter counts 3 twelve input pulses, it will return to the O state, with the logical output 1 signal again at the first output of the decoder 4, corresponding to the count twelve, which will return the second RS flip-flop 8 to the logical O state (FIG. 2k). And again, when the count is equal to three, corresponding to the arrival of the fifteenth pulse counting at the input of counter 3, the fourth output of the decoder 4 has a logical 1 signal, which sets the fourth RS flip-flop

10 in the state of logical O.

With the installation of all RS-triggers 7-10 in the state of logical O.

one

element 4W 12 will generate a logical O signal, which will return counter 3 to the initial zero state.

Thus, the cycle of formation of control pulses (Fig, 2h, and, k, l) will be completed. Connecting the second and third outputs of the decoder 4 (pins 1 and 2) to the inputs of the ZILI 11 element is necessary for organizing (starting) the possible start of the next cycle of operation not only with an account equal to twelve, but also with accounts equal to thirteen or fourteen.

By changing the value of the control code 19 (by changing the division ratio of the controlled frequency divider 2), the arrival time of the Pulses from the output of the frequency divider 2 will change, which will lead to the regulation of the pause between two polarized pulses (Fig. 2m). Tn T; N ;, where Tj is the period of arrival

0

five

0

lazy pulses from the output of the master oscillator 1.

The thus-generated control signals from the direct outputs of the RS flip-flops 7-10 control the switching mode of the first 14 and second 15 key amplifiers.

The rotation of the direction of rotation of the motor 16 is carried out by changing the order of the input pulses by means of a control switch 13 under the influence of the control signal 20.

Thus, with sufficient simplicity of implementation, the device provides the required accuracy and discreteness of controlling the rotation frequency and torque of a two-phase asynchronous electric motor.

Claims (1)

Invention Formula A two-phase motor control device comprising a controlled frequency divider, a serially connected counter and a decoder, a master oscillator, the output of which is connected to the inputs of a controllable frequency divider and counter, four RS flip-flops, two And elements, two key amplifiers whose outputs are designed for connecting to terminals, respectively, an excitation winding, and a control winding of a two-phase electric motor, the inputs of the first key amplifier are connected to the codes of the first and second E8-trigger in ode second key amplifier through a switch connected to the outputs of the third and fourth RS flip-flops, characterized in that, with the chain of simplifications introduced therein Zili element and 4SHSH element whose inputs are connected to outputs corresponding RS-flip-flops, and the output of the 4ShSh element is connected to the installation input to the O / counter, the output of the controlled frequency divider is connected to the first input of the first And element whose output is connected to the S input of the first RS-flip-flop, the R input of which is combined with S-input of the second RS-flip-flop, the second input of the first element And is connected to the output of the element ZILI, the inputs of which are connected to the first, second and third outputs of the decoder, the first output of the decoder is connected to the R-input of the second RS-flip-flop, the fourth output of the decoder is connected to the first input of the second element I and to the R-BHOD of the fourth short-circuit trigger, the fifth output of the remote controller is connected to the R input of the first RS trigger, the output of which is connected to the second input the second element And, the output of which is connected to the S-input of the third RS-flip-flop, the R-input of which is combined with the S-input of the fourth RS-flip-flop and connected to the sixth output of the decoder.