SU1681382A1 - Digital frequency synthesizer - Google Patents

Abstract

The invention is fire engineering. The aim of the invention is to increase speed. The digital frequency synthesizer contains a controlled oscillator 1, a divider 2 frequencies with a variable division factor, a frequency-phase detector 3. a reference oscillator 4, a divider 5 frequencies with a fixed division factor, current generators 6 and 9, current switches 7 and 10, filter 8 lower frequencies, memory bout 11, code comparison block 12, write pulse shaper 13, elements OR 14 and 15 When switching to a new frequency, a signal of unequalities is generated at the first output of block 12 by comparing new and old frequency codes. Depending on whether the new code is more or less, OR 14 and 15 elements receive pulses at the control input of the current switch 7 or 10. The goal is achieved due to the fact that when switching frequencies, not waiting for the divider 2 counting cycle, a restructuring occurs controlled generator 1 in the right direction due to the forced control of keys 7 and 10 1 sludge

Description

b

The invention relates to radio engineering and can be used in transceiver and control instrumentation.

The purpose of the invention is to increase speed.

The drawing shows a structural electrical circuit of a digital frequency synthesizer.

The digital frequency synthesizer contains a controlled oscillator 1, a divider 2 with a variable division factor (DPKD), a frequency-phase detector (FFD) 3, a reference oscillator 4, a frequency divider 5 with a fixed division factor (DFCD), the first current generator 6, first current key 7, low pass filter 8, second current generator 9, second current key 10, memory block 11, code comparison unit 12, write pulse driver 13, first element OR 14, second element OR 15.

Digital frequency synthesizer works as follows.

In synchronization mode, short impulses are formed at the outputs of the FPD 3, which almost coincide with one another in time. These impulses pass through the first element OR 14 to the first current switch 7, and through the second element OR 15 to the second current switch 10, which opens a short time and an almost simultaneous charge - discharge of the capacity of the filter 8 is carried out so that the control voltage at the output of the filter 8 is almost unchanged. At the same time, in DPCD 2, memory block 11 and comparison block 12, the same frequency control code is recorded at the control input.

When switching to a different frequency, a new code is supplied to the control input of the comparison unit 12. 8, the result of comparing the old code from the memory block 11 and the new code on the first output of the comparison block 12 forms an unequal signal, which is fed to the input of the imaging unit 13, the output of which produces a pulse, which is fed to the reset input of the PDDK 2, DFCD 5 and the recording resolution code in memory block 11. The signal of inequality is proportional to the difference of the codes, t, e,

D I Ebp-En I,

where abp is the code located in memory block 11;

an - new code;

L is the code corresponding to the magnitude of the signal of disparity.

Depending on whether the new code is greater or less, from the second or third

the output of the comparator unit 12, respectively, through the first or second element OR 14, 15, a pulse arrives at the control input of the first or second current switch 7, 10. The corresponding current switch opens for a time equal to the duration of the output pulse of the driver 13, and a forced charge or discharge occurs d of the filter capacity 8, which causes a forced restructuring of the controlled generator 1 in the desired direction. The response time of the first or second current switch 7, 10 is equal to the pulse duration from the output of the imaging unit 13. which is determined by the magnitude of the unequality signal. At the end of the output pulse of the imaging unit 13, a new code is generated at the output of the memory unit 11, which is fed to the comparison unit 12. As a result, at the first output of the comparison unit 12, an equivalence signal is formed, and at the second and third outputs, the signals permitting the passage of the first and second elements OR 14, 15 control pulses from 5 corresponding outputs of the FFD 3. At the same time, the PDDK 2 and DFCD 5 start a new the input pulse count, and the usual operation of the digital frequency synthesizer takes place in a state close to synchronism. Q Thus, as soon as a command is received to switch frequencies (a new control input code of a digital frequency synthesizer), do not wait for the end of the DPKD counting cycle, the controlled oscillator 1 is reorganized in the right direction, and the forced control of the first and second current keys 7, 10 occurs at any misalignment.

Claims (1)

The digital frequency synthesizer allows 0 to increase the speed with a simple circuit implementation, especially in the case of small changes in the control code. DETAILED DESCRIPTION OF THE INVENTION A digital frequency synthesizer comprising a series-connected reference oscillator, a frequency divider with a fixed division factor, and a frequency-phase detector, the first current generator connected in series, the first current switch, the low-pass filter, the variable oscillator, and the frequency divider. the division factor, the output of which is connected to the second input of the frequency-phase detector, 5 serially connected second current generator, and the second current switch, the output of which is connected To the input of the low-pass filter, as well as the first and second elements OR, characterized in that, in order to improve speed, serially connected write pulse shaper, memory block and code comparison block are introduced, the first output of which is connected to the code input of the write pulse shaper whose output is connected to the reset input of a frequency divider with a variable division factor and to the reset input of a frequency divider with a fixed division factor, the second output of the code comparison unit is connected to the first input the first element OR, the second input and output of which are connected respectively to the first output 0 the frequency-phase detector and the control input of the first current switch, the third output of the code comparison unit is connected to the first input of the second OR element, the second input and output of which are connected respectively to the second output of the frequency-phase detector and the control input of the second current switch The control inputs of a frequency division divider with a variable division factor, a code comparison unit and a memory unit are combined to be the control input of a digital frequency synthesizer.