JPS63110816A - Oscillation circuit - Google Patents
Oscillation circuitInfo
- Publication number
- JPS63110816A JPS63110816A JP61257358A JP25735886A JPS63110816A JP S63110816 A JPS63110816 A JP S63110816A JP 61257358 A JP61257358 A JP 61257358A JP 25735886 A JP25735886 A JP 25735886A JP S63110816 A JPS63110816 A JP S63110816A
- Authority
- JP
- Japan
- Prior art keywords
- oscillation
- circuit
- input
- oscillation circuit
- inverter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000010355 oscillation Effects 0.000 title claims abstract description 88
- MEGPURSNXMUDAE-RLMOJYMMSA-N scopoline Chemical compound C([C@H](O1)C2)[C@@H]3N(C)[C@H]2[C@H]1[C@H]3O MEGPURSNXMUDAE-RLMOJYMMSA-N 0.000 abstract 2
- 238000009434 installation Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 6
- 238000009412 basement excavation Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は発振回路に関し、特に直ちに発振を停止させ、
かつ正確な発振開始を行なうことができるものに関する
ものである。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an oscillation circuit, and in particular, to an oscillation circuit that immediately stops oscillation,
The present invention also relates to a device capable of accurately starting oscillation.
発振回路において発振停止状態及び発振状態を繰り返す
場合に用いられる従来の回路を第３図に示す。FIG. 3 shows a conventional circuit used when an oscillation circuit repeats an oscillation stop state and an oscillation state.
第３図において、発振回路はインバータ１，３．２入力
ＮＡＮＤゲート２、及び抵抗値Ｒｓ、Ｒｆの抵抗４，５
から構成される。インバータ１の入力側と２入力ＮＡＮ
Ｄゲート２の出方側とは抵抗５を介して接続されており
、この接続と抵抗５とによりシュミット構成の発振回路
が形成されている。In FIG. 3, the oscillation circuit consists of inverters 1, 3.2 input NAND gate 2, and resistors 4 and 5 with resistance values Rs and Rf.
It consists of Input side of inverter 1 and 2 input NAN
It is connected to the output side of the D gate 2 via a resistor 5, and this connection and the resistor 5 form a Schmitt configuration oscillation circuit.
なお、発振停止パルス信号は２入力ＮＡＮ４Ｄゲート２
の一方に接続されている。また、ＲＯは抵抗、ＣＯはコ
ンデンサで、発振回路の外付回路である。Note that the oscillation stop pulse signal is the 2-input NAN4D gate 2.
connected to one side. Further, RO is a resistor and CO is a capacitor, which are external circuits of the oscillation circuit.
次に動作について説明する。Next, the operation will be explained.
発振回路は発振振幅がＲｆとＲｓの比で決まるシュミッ
ト回路構成となっているため、第４図中）に示すように
電源電位ＶＤＤと接地電位Ｖｓｓ間中の“Ｈ”のスレッ
シュホルドレベルＶ ＴＨＨと“Ｌ”のスレッシュホル
ドレベルＶ ＴＨＬ間を、外付抵抗ＲＯ１外付コンデン
サＣＯで決まる充放電で発振する。Since the oscillation circuit has a Schmitt circuit configuration in which the oscillation amplitude is determined by the ratio of Rf and Rs, the "H" threshold level V THH between the power supply potential VDD and the ground potential Vss, as shown in Figure 4). It oscillates between the "L" threshold level V THL and the charging/discharging determined by the external resistor RO1 and the external capacitor CO.
発振を停止させる場合は、発振停止パルスを第４図（ａ
ｌのように入力すればよく、これにより、２入力ＮＡＮ
Ｄゲート２の出力は“Ｈ”レベルになり、発振回路の出
力端子０３ＣＯＵＴはこの“Ｈ″レベルインバータ３を
経由するため“Ｌ”レベルになり、発掘回路の入力端子
０ＳＣＩＮも第４図（ｂ）のように“Ｌ”レベルとなり
発振が体止することとなる。しかるに実際には完全に発
振が停止するのはこの発振回路がもつ停止に至るまでの
遅延時間の後であり、発振停止パルス出力直後に直ちに
発振を停止させることはできない、また、この発振停止
パルスが短い場合には入力端子０３ＣＩＮの電位により
、発振スタート時の時間が異なるため正確な発振開始を
行なうことはできない。To stop oscillation, set the oscillation stop pulse as shown in Figure 4 (a).
You just have to input it like l, and by doing this, 2-input NAN
The output of the D gate 2 becomes "H" level, the output terminal 03COUT of the oscillation circuit goes through this "H" level inverter 3 and becomes "L" level, and the input terminal 0SCIN of the excavation circuit also becomes "L" level as shown in Fig. 4 (b). ), the signal goes to "L" level and oscillation stops. However, in reality, oscillation completely stops only after the delay time of this oscillation circuit until it stops, and oscillation cannot be stopped immediately after the oscillation stop pulse is output. If 03CIN is short, the time at which oscillation starts differs depending on the potential of input terminal 03CIN, making it impossible to start oscillation accurately.
従来の発振回路は以上のよう、に構成されており、発振
を停止させるためには、余振ｆ挙止パルス時間を大きく
する必要があり、この発振停止パルス時間が短時間の場
合は、発振停止の後、正確で安定な発振開始を行なうこ
とはできないという問題点があった。Conventional oscillation circuits are configured as described above. In order to stop oscillation, it is necessary to increase the aftershock f-stop pulse time. If this oscillation stop pulse time is short, the oscillation stops. There is a problem in that accurate and stable oscillation cannot be started after stopping.
本発明はこのような従来のものψ問題点に鑑みてなされ
たもので、その目的セは発振停止の後、正確で安定な発
振開始を行なうことができ、かつその位相合わせを行な
うことができる発掘回路を提供することにある。The present invention was made in view of the problems of the conventional ψ, and its purpose is to be able to accurately and stably start oscillation after stopping oscillation, and to perform phase matching. The purpose is to provide an excavation circuit.
本発明に係る発振回路は発振回路の人、出力端子にそれ
ぞれＮチャネルＭＯ３ＦＥＴ （電界効果トランジスタ
）を接続し、これを発振停止パルスで制御することによ
り、短時間での発振停止と、正確で安定な発振開始とを
行なうことができるように構成したものである。The oscillation circuit according to the present invention connects N-channel MO3FETs (field effect transistors) to the output terminals of the oscillation circuit, and controls them with oscillation stop pulses to stop oscillation in a short time and accurately and stably. The structure is such that it is possible to start oscillation.
（作用〕
本発明においては、発振停止時には発振停止パルス信号
が発振回路の人、出力部にそれぞれ設けたＮチャネルＭ
Ｏ３ＦＥＴをオンさせ、発振回路の入力及び出力が直接
Ｖｓｓに固定される。従って発振回路内部からの遅延時
間がなく、発振回路を短時間で発振停止させることがで
き、また発振停止パルス終了後は、正確な発振開始を行
なわせることができる。(Function) In the present invention, when the oscillation is stopped, the oscillation stop pulse signal is sent to the N-channel M
The O3FET is turned on and the input and output of the oscillation circuit are directly fixed to Vss. Therefore, there is no delay time from inside the oscillation circuit, the oscillation circuit can be stopped in a short time, and oscillation can be started accurately after the oscillation stop pulse ends.
以下、本発明の一実施例を図について説明する。 Hereinafter, one embodiment of the present invention will be described with reference to the drawings.
第１図は本発明の一実施例による発振回路を示し、図に
おいて、８．９は発振停止時に人、出力端子０ＳＣＩＮ
、 ０ＳＣＯＵＴの電位をともに接地電位Ｖｓｓにする
ためのＮチャネルＭＯＳトランジスタである。FIG. 1 shows an oscillation circuit according to an embodiment of the present invention. In the figure, when oscillation is stopped, the output terminal 0SCIN
, 0SCOUT are both N-channel MOS transistors for setting the potentials of 0SCOUT to the ground potential Vss.
次に動作について第２図の動作波形図を用いて説明する
。第２図中の（イ）、（ロ）はそれぞれ第１図のインバ
ータ６．２入力ＮＡＮＤ回路２の出力である。Next, the operation will be explained using the operation waveform diagram in FIG. 2. (A) and (B) in FIG. 2 are the outputs of the inverter 6.2 input NAND circuit 2 of FIG. 1, respectively.
本回路の発振時の動作は第１図の従来回路と同様である
が、本実施例゛では上記ＮチャネルＭＯＳトランジスタ
８，９を設けているので、入力端子０ＳＣＩＨの電位は
第２図（０）に示すように発振停止のＴｄ期間は接地電
位Ｖｓｓになる。そして発振開始の始まりは正確に接地
電位から電位の充電が開始されることとなり、図に示す
ような発振状態で次段のインバータ１が応答して発振が
開始される。The operation of this circuit during oscillation is similar to that of the conventional circuit shown in FIG. ), the ground potential is Vss during the Td period when oscillation is stopped. At the beginning of oscillation, charging of the potential from the ground potential is precisely started, and the inverter 1 at the next stage responds to start oscillation in the oscillation state shown in the figure.
ここで発振停止時は出力端子０５ＣＯＵＴの電位もＮチ
ャネルＭＯＳトランジスタ９によってＶｓａレベルに固
定されるため、従来のように２入力ＮＡＮＤゲート２の
応答でインバータ３が応答して出力端子０ＳＣＯＵＴの
レベルを固定する場合に比べて内部遅延が少な（、この
ため発振停止パルスは従来技術よりも短いもので可能で
ある。When the oscillation is stopped, the potential of the output terminal 05COUT is also fixed at the Vsa level by the N-channel MOS transistor 9, so the inverter 3 responds in response to the 2-input NAND gate 2 and changes the level of the output terminal 0SCOUT, as in the conventional case. The internal delay is smaller than in the fixed case (therefore, the oscillation stop pulse can be shorter than in the prior art).
このように本実施例では、従来の発振停止パルスに比べ
て短いパルス中のパルスで発振回路を停止させ、発振回
路の発振開始を正確に行なわせることができる。As described above, in this embodiment, the oscillation circuit can be stopped with a pulse that is shorter than the conventional oscillation stop pulse, and the oscillation circuit can be started to oscillate accurately.
なお、ここで発振回路にはＣＲ発振を用いたが、これは
他の外付回路による発振を行なっても同様な効果を奏す
る。Although CR oscillation is used here as the oscillation circuit, the same effect can be achieved even if oscillation is performed using another external circuit.
以上説明したように、本発明に係る発振回路によれば、
発振回路の人、出力端子にそれぞれＮチャネルＭＯ３Ｆ
ＥＴ （電界効果トランジスタ）を接続し、これを発振
停止パルスで制御するようにしたので、短い発振停止パ
ルス巾で直ちに発振を停止させることができるとともに
発振開始を安定かつ正確に行なわせることができ、発振
回路において発振の停止と開始を頻繁に要する場合に番
特に効果がある。As explained above, according to the oscillation circuit according to the present invention,
N-channel MO3F for each oscillation circuit and output terminal
Since an ET (field effect transistor) is connected and controlled by an oscillation stop pulse, oscillation can be stopped immediately with a short oscillation stop pulse width, and oscillation can be started stably and accurately. This is particularly effective when stopping and starting oscillation is required frequently in an oscillation circuit.
第１図は本発明の一実施例による発振回路の回路図、第
２図は第１図の動作波形図、第３図は従来の発振回路を
示す回路図、第４図は第３図の動作波形図である。
１．３，６．７・・・インバータ、２・・・２入力ＮＡ
ＮＤゲート、４．５・・・抵抗、８．９・・・ＭＯＳＦ
ＥＴ、 ０５ＣＩＮ・・・発振回路入力端子、０３ＣＯ
ＵＴ・・・発振回路出力端子。Fig. 1 is a circuit diagram of an oscillation circuit according to an embodiment of the present invention, Fig. 2 is an operation waveform diagram of Fig. 1, Fig. 3 is a circuit diagram showing a conventional oscillation circuit, and Fig. 4 is a circuit diagram of Fig. 3. It is an operation waveform diagram. 1.3, 6.7...Inverter, 2...2 input NA
ND gate, 4.5...Resistance, 8.9...MOSF
ET, 05CIN...Oscillation circuit input terminal, 03CO
UT...Oscillation circuit output terminal.
Claims (1)
続された第１のインバータと、 その一方の入力が該第１のインバータの出力に接続され
その出力が第２のインバータの入力に接続されるととも
に発振回路の出力端子を構成する２入力ＮＡＮＤゲート
と、 該２入力ＮＡＮＤゲートの出力と上記第１のインバータ
の入力との間に接続された抵抗とを備えた発振回路にお
いて、 上記入力端子及び出力端子にそれぞれ接続されたＮチャ
ネルＭＯＳトランジスタと、 該両ＮチャネルＭＯＳトランジスタを制御するための発
振停止パルスを発生する手段とを備えたことを特徴とす
る発振回路。(1) A first inverter whose input is connected to the input terminal of the oscillation circuit via a resistor, and one input of which is connected to the output of the first inverter and whose output is connected to the input of the second inverter. An oscillation circuit comprising: a 2-input NAND gate connected to the oscillation circuit and forming an output terminal of the oscillation circuit; and a resistor connected between the output of the 2-input NAND gate and the input of the first inverter; An oscillation circuit comprising: an N-channel MOS transistor connected to an input terminal and an output terminal, and means for generating an oscillation stop pulse for controlling both the N-channel MOS transistors.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61257358A JPH07120939B2 (en) | 1986-10-28 | 1986-10-28 | Oscillator circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61257358A JPH07120939B2 (en) | 1986-10-28 | 1986-10-28 | Oscillator circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63110816A true JPS63110816A (en) | 1988-05-16 |
| JPH07120939B2 JPH07120939B2 (en) | 1995-12-20 |
Family
ID=17305272
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61257358A Expired - Lifetime JPH07120939B2 (en) | 1986-10-28 | 1986-10-28 | Oscillator circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07120939B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02192309A (en) * | 1989-01-20 | 1990-07-30 | Nec Corp | Oscillation circuit |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5972219A (en) * | 1982-10-18 | 1984-04-24 | Nec Corp | Cr oscillator |
-
1986
- 1986-10-28 JP JP61257358A patent/JPH07120939B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5972219A (en) * | 1982-10-18 | 1984-04-24 | Nec Corp | Cr oscillator |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02192309A (en) * | 1989-01-20 | 1990-07-30 | Nec Corp | Oscillation circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH07120939B2 (en) | 1995-12-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4039973A (en) | Initiation circuit in a crystal-controlled oscillator | |
| JPS6232846B2 (en) | ||
| JPS6367822A (en) | Oscillator | |
| JPH10163829A (en) | Noise eliminating circuit for oscillator | |
| JPH04115622A (en) | Current mirror type amplifier circuit and driving method therefor | |
| JPS59175218A (en) | Cmos inverter | |
| JPS63110816A (en) | Oscillation circuit | |
| JP2551871B2 (en) | Oscillation control circuit | |
| EP0234306A2 (en) | Oscillator with feedback loop including delay circuit | |
| JP2803448B2 (en) | Output circuit | |
| JPS63117512A (en) | Oscillation circuit | |
| JP2690694B2 (en) | Parallel CMOS inverter oscillator circuit | |
| JPS63172505A (en) | Cmos gate array osclllation circuit device with oscillation stop function | |
| KR100319641B1 (en) | Circuit for generrating constant voltage | |
| KR910000192B1 (en) | Voltage controled oscillator using mos | |
| JP3358379B2 (en) | CMOS piezoelectric oscillation circuit | |
| JPS6243367B2 (en) | ||
| JPH01106505A (en) | Oscillation circuit | |
| JPS6230524B2 (en) | ||
| JPH04273602A (en) | Oscillation control circuit | |
| JPS63113716A (en) | Power-on resetting circuit | |
| JPS5992620A (en) | Clock generator circuit | |
| JPH048668Y2 (en) | ||
| JPS5936445B2 (en) | Low power circuit | |
| JPS58136136A (en) | Intermittent drive type time constant circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313111 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| EXPY | Cancellation because of completion of term |