JPS5936445B2 - Low power circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a complementary insulation effect transistor (hereinafter referred to as CMO8).
The purpose is to reduce the power consumed by the circuit.

A detailed explanation will be given below based on the drawings. FIG. 1 shows a conventional CMO8 oscillation circuit.

The input end and the output end of the CMOS inverter 1 are connected through a feedback resistor 2, and the output end is connected to one terminal of a vibrator 3 and one terminal of an output capacitor 5 via an output resistor 6.

The remaining terminal of the vibrator 3 is connected to the input end of the inverter 1 and grounded via the input capacitor 4.

One remaining terminal of the output capacitor 5 is grounded.

FIG. 2 shows the transfer characteristic of the inverter 1 in FIG. 1, and point P represents the bias potential due to the feedback resistor.

In the oscillation state, the input potential changes around reading point P, but near point P a through current flows as shown by the broken line in the figure, so the power consumed by the oscillator is extremely large.

This through current can be reduced by increasing the threshold voltage of the transistor, but this is often not possible.

For example, in an electronic timepiece that drives a step motor, the motor drive transistor is required to have an extremely large current capacity.

Therefore, a method is required to reduce the on-resistance by increasing the channel width of the transistor, but at this time, the influence of the threshold voltage affects the value of the on-resistance as a square term.

That is, in order to minimize the area occupied by the drive transistor, it is desirable that the threshold voltage be as low as possible.

On the other hand, it is difficult to manufacture transistors with different threshold voltages within the same integrated circuit.

Therefore, the threshold of the oscillation transistor is often made the same as that of the drive transistor.

Therefore, as a way to reduce the through current in the oscillation circuit,
Either reduce the conductance of the oscillation transistor, or
Alternatively, as shown in FIG. 3, a method may be used in which a resistance element is inserted in series with the channel of the transistor.

In the circuit shown in Figure 3a, when the value of the resistor is R and the current consumed when configuring the same oscillation circuit as in Figure 1 is IQ, the relationship between the two is as shown in Figure 4. Thus, by setting the position of R to a large value, the current consumption can be made sufficiently small.

However, the oscillation output will eventually be supplied to a CMOS gate circuit as a load, and current consumption should be considered including this load.

The type of load connected varies depending on the case, but it can generally be represented by one inverter.

Therefore, as shown in FIG. 5, the oscillation circuit 7 is loaded with CM.
When the OS inverter 8 is connected and the relationship between the resistance value R and the current consumption IQ is determined as before, as shown in FIG. 6, when the resistance value R is increased, the current consumption decreases at first and then increases.

This is because when R is increased, the power to drive the vibrator decreases, the vibration amplitude gradually decreases, the rise and fall times of the oscillation output increase, and the amplitude further decreases, so the through current flowing through the inverter 8 This is because the amount increases rapidly.

If the inverter 8 is configured as shown in FIG. 3, the through current of the inverter 8 will be reduced, but the rise and fall times of the output waveform will become longer, and the same problem as described above will occur for the subsequent load.

The present invention takes the above matters into consideration and attempts to obtain the minimum power consumption including the oscillation circuit and the load.

FIG. 7 shows an embodiment of the present invention, in which transistors 9 and 10 are connected in series to the power supply path of the load gate circuit 8, and the gate of the transistor is connected to the power supply side, which is a fixed potential section, via a capacitor 11. and the gate circuit 8 via the resistor 12.
Connect to the output end of the

FIG. 8 shows operating waveforms of the configuration of FIG. 7.

Oscillator output A is inverted and amplified by inverter 8 and appears at point B.

At point C, based on the time constant due to capacitor 11 and resistor 12,
The waveform at point B is transmitted.

Current I passing through inverter 8 and transistors 9 and 10
Q is the penetration timing of inverter 8 and transistor 9
, 10 due to the phase difference with the penetration timing.

It can be seen from FIG. 8 that the current consumption IQ decreases by 20.

The embodiment shown in FIG. 7 has very good rise and fall characteristics.

Further, by reducing the value of the resistor 12, the amplitude of the signal at point B can be reduced, so that the current consumption of the capacitive load can be further reduced.

Note that the capacitance 11 can be replaced by the gate capacitance of the transistors 9 and 10.

Further, the transistors 9 and 10 may be inserted on the drain side of the transistors forming the gate circuit 8.

In the embodiment described above, the through current of the oscillation circuit is suppressed by inserting a resistor into the power supply path of the inverter, which reduces the conductance of the oscillation amplification inverter, and as a result, the oscillation output waveform deteriorates. The main focus has been on how to limit the through current flowing through the gate circuit driven by the output waveform.

However, the point of reducing through current is the same for both oscillation inverters and simple gate circuits; the difference is that in oscillation inverters, both channel transistors flow current when oscillation starts. The only additional condition is that it must be biased toward the state that it obtains.

Therefore, if this condition is satisfied, each of the embodiments described above can be applied to an oscillation circuit.

FIG. 9 shows an example in which the embodiment shown in FIG. 7 is applied to an oscillation inverter.

In this case, during the rise and fall times of the output, the one of the control transistors through which current should flow is sufficiently turned on, so the rise and fall characteristics are very good.

Therefore, flip and flop circuits that require input with fast rise and fall characteristics can also be driven without a buffer circuit.

As described above, according to the present invention, the power consumed by the circuit can be reduced, which is advantageous for small electronic devices such as watches.

Note that it goes without saying that the present invention may be implemented in any combination, and for the sake of simplicity, an inverter is shown as a logic circuit, but this may also be a logic circuit with other functions. Of course, this is a matter of course.

Further, in the circuit shown in FIG. 7, the gates of the transistors 9 and 10 may be connected to the output end through different resistors, as shown in FIG. 10.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing a typical example of a crystal oscillator using CMOS transistors, Figure 2 is a characteristic diagram of a CMOS inverter, Figures 3a and b are conventional current limiting circuit diagrams, Figures 4 and 4 are Fig. 6 is a current consumption characteristic diagram of a conventional circuit, Fig. 5 is an oscillation circuit diagram with a load, Fig. 7 is a circuit diagram showing an embodiment of the present invention, Fig. 8 is an operation waveform diagram of Fig. 7, and Fig. 9 10 are circuit diagrams showing still another embodiment of the present invention. 9.10... Current control transistor, 7...
...Oscillation circuit, 8...Gate circuit, 12.
...Resistance element.

Claims (1)

[Scope of Claims] 1. An insulated gate field effect transistor for current control is provided in the power supply line of a logic circuit having at least one input terminal and one output terminal and composed of complementary insulated gate field effect transistors. are connected in series, and the output end of the logic circuit is connected to the gate side of the current control insulated gate field effect transistor via a resistor, and the gate side is connected to a fixed potential section via a capacitor. A low power circuit characterized by: 2. The power saving circuit according to claim 1, wherein at least one input terminal is connected to an output terminal of the oscillation circuit.