JPH01118890A - Bit map memory apparatus - Google Patents

Abstract

PURPOSE: To execute one swap processing in three memory cycles to increase the swap processing speed by performing the read modify write operation of a bit map memory. CONSTITUTION: Data in a first area A is read out from a bit map memory 20 in the first half of a first memory cycle, and this data is written in a second area B in the latter half of a second memory cycle after being held in a second holding means 22 through a first holding means 21. Data in the second area B is read out from the bit map memory 20 in the first half of the second memory cycle, and this data is written in the first area A in the latter held of a third memory cycle after being held in the second holding means through the first holding means 21. Thus, one swap processing is executed in three memory cycles, and it is unnecessary to switch a data bus in each cycle.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a pit map memory device equipped with a bit map memory, and in particular, the present invention relates to a pit map memory device having a bit map memory. Pit image swap method (prior art) In general, in a pit map display device, etc., the contents of an area A on the pit map memory 10 shown in FIG. 4 are swapped with the contents of another area B. The contents may be swapped. Conventionally, this type of swap processing involves preparing a pair of temporary registers 11 and 12 as shown in FIG.
The contents (A1) of (+-0, 1...) are stored in register 1.
Read to 1.

■ Address 3i of area B on pit map memory 10
The contents (Bi) of (i-0, 1...) are stored in register 1.
Read out to 2.

■ Write the contents of register 12 to address A1 of area A.

■ Write the contents of register 11 to address B1 of area B.

This was done by repeating a swap cycle consisting of steps ① to ②. The address (to the pit map memory 10) and the read/write data (to the pit map memory 10) in this swap process are as shown in FIG.

The conventional swap method described above requires four memory cycles for one swap process, and there is a problem in that it is difficult to speed up the process. In addition, two - time registers are required, and since the data buses for each memory cycle from ■ to ■ are all different, the read data from pit map memory 10 is switched and output to either register 11 or 12. This requires a demultiplexer to switch and output the contents of either register 11 or 12 to pit map memory 10, and the circuit configuration around the pit map memory becomes complicated.

(Problem to be solved by the invention)) As mentioned above, conventionally, one swap process on pit map memory requires four memory cycles, and each cycle uses a different data bus, resulting in high-speed processing. In addition to being difficult to implement, there is a problem in that the circuit configuration around the pit map memory is complicated.

The present invention has been made in view of the above circumstances, and its object is to provide a pit map device that can perform swap processing of pit images such as figures on a bit map memory at high speed and with a simple circuit configuration.

[Structure of the Invention] (Means for Solving the Problems) The present invention includes a first holding means for holding data read out from a pit map memory, and a method for storing data held in the first holding means for external output or for next generation. a second holding means for holding data for write processing to the pit map memory in a memory cycle; and a first holding means for switching data held in the second holding means or external write data for writing processing to the pit map memory. a multiplexer, first and second address generation circuits that generate addresses of first and second areas to be swapped on the bitmap memory, and a second multiplexer that switches outputs of the first and second address generation circuits. , a control means for repeatedly swapping the image data between the first and second areas in three cycles of the first to third memory cycles by operating the pit map memory in a read-modify-write manner; In the third memory cycle, the address from the first address generation circuit is used as the address to the pit map memory, and in the second memory cycle, the address from the second address generation circuit is used as the address to the pit map memory.
It is characterized in that the output is switched from a multiplexer.

(Function) According to the above configuration, in the first half of the first memory cycle, the data of the first area is retrieved from the pit map memory, and this data is held in the second holding means via the first holding means. , is written to the 21I area in the second half of the next second memory cycle. Also, in the first half of the second memory cycle, data in the second area is read from the bitmap memory, and this data is held in the second holding means via the first holding means, and then in the second half of the next third memory cycle. Written to the first area. That is, according to the above configuration, one swap process can be performed in three memory cycles, and there is no need to switch the data bus every cycle.

(Embodiment) FIG. 1 shows a block configuration of a bitmap memory device according to an embodiment of the present invention. In the figure, 20 is a bitmap memory (bitmap memory element) that stores figures, images, etc., and 21 is a transparent latch that holds -H data at the read timing when the bitmap memory 20 is operated in a read-modify-write cycle. (hereinafter simply referred to as latch), 22
bitmap memory 2 supplied via latch 21
A read data register (hereinafter referred to as RDR) that temporarily holds read data from 0; 23 is a driver for sending the read data held in RDR22 to a system bus (not shown); 24 is data from the system bus. This is a receiver for importing the data into a bitmap memory device.

Reference numeral 25 denotes a multiplexer (hereinafter referred to as "multiplexer") that switches between using data from the system bus supplied via the receiver 24 or returning read data held in the RDR 22 as data for write processing to the bitmap memory 20. MLIX), 26 is an arithmetic circuit (hereinafter referred to as raster operation) that performs an operation (raster operation) between the data from the MLJX 25 and the read data from the latch 21.
(referred to as ALU). The ALLI 26 has a through function that allows input data to pass through as is.

27 is an address generation circuit that generates an address for one area (area A here) to be swapped on the bitmap memory 20, and 28 is an address generator that generates an address for the other area (area B here). It is a circuit. Reference numeral 29 connects the output of either the address generation circuit 27 or 28 to the bitmap memory 20 (address input).
MUX (multiplexer) for switching connection to
30 is bit block transfer (bi
tbit)) (hereinafter referred to as bitb)
(referred to as the IT control circuit). The bitblt control circuit 30 outputs a control signal for updating addresses to the address generation circuits 27 and 28, outputs a switching control signal for controlling switching of the MLJX 29, and outputs a switching control signal for controlling the switching of the MLJX 29.
It is designed to output a write pulse to 0, etc.

Note that, in FIG. 1, a barrel shifter and a merge circuit for enabling bit boundary access to the pit map memory 20 are omitted.

Next, the operation of the configuration shown in FIG. 1 will be explained using the case where the contents of area A on the bitmap memory 20 are swapped with the contents of another area B as shown in FIG. 2, as shown in FIG. 3. This will be explained with reference to the timing chart.

First, the address generation circuits 27 and 28 generate addresses Ai of areas A and B on the bitmap memory 20.

Setup is performed by a control means such as a microprocessor (not shown) to generate Bi(i-Q, 1, . . . ). Further, the MUX 25 is set to select the read data from the RDR 22, and the ALU 26 is set to pass the left input content, that is, the output data of the MLJX 25. It's like this, bitbltlJ
Il] Circuit 3G H M U X29eIIJ Ij L,
, in the first memory cycle T1, the address generation circuit 2
1 (in this case, the address AO at the beginning of area A) is selectively output to the pit map memory 20.

The bitmap memory 20 operates on a read-modify-write cycle.

Therefore, in the first half of the cycle in the read mode (the first half of Tl), the address AO from the address generation circuit 27 is
One word data of the area A designated by , ie, the contents of the address AO (AO), is read out from the pit map memory 20 as shown by ■ in FIGS. 2 and 3, and then latched into the latch 21. The contents of the address AO latched by the latch 21 are R
Moved to DR22. That is, in cycle T1,
Reading from area A is performed, and the read data (in this case, the contents of address AO) is latched into RDR 22 (see ◯ in FIGS. 2 and 3).

Although the bitmap memory 20 operates at the read-modify-write timing as described above, no write operation is performed at T1. Therefore, in this embodiment, in a normal read-modify-write cycle, a write pulse is given from the bitblt control circuit 30 to the pit map memory 20 in the second half, but in the memory cycle (T1) where only reading is required, Ha, bltbltl! Write pulse output from the I control circuit 30 to the pit map memory 20 is prohibited.

When memory cycle T1 ends, bitbIt
IIJIl [[301tM U X29e 7 )'
The address is switched to the main circuit 2B side of the main circuit 2B, and the address from the circuit 28 (in this case, the address BO at the head position of area B) is selectively output to the pit map memory 2G. As a result, in the first half of the next memory cycle T2, one of the areas B specified by the address BO is extracted from the pit map memory 20.
The word data, that is, the contents of address 80 (BO) is the second
The data is read out as shown by ■ in FIGS. 3 and 3, and then latched into the latch 21.

Now, the contents of the address AO read from the pit map memory 20 and latched to the launch 21 in the first half of the memory cycle T1, and transferred to the RDR22 in the second half are the MLJX (set in the RDR22 selection mode).
25, AL (set to left input through mode)
The data is supplied to the pit map memory 20 as write data via U26. As a result, the contents of the address AO from the RDR 22 are transferred to the address BO of the area B of the pit map memory 20 operating in the read-modify-write cycle in the latter half of the memory cycle T2 as shown in FIGS.
It is written as shown by ■ in the figure. At the same time (or with a slight delay), the contents of the address BO, which was read from the pit map memory 20 and latched in the latch 21 in the first half of T2, is transferred to the RDR 22 (see (2) in FIGS. 2 and 3).

When the memory cycle T2 ends, the bitblt control circuit 30 switches the MLIX 29 to the address generation circuit 2761 again, and selectively outputs the address from the circuit 27 (here, the address AO of area A) to the pit map memory 20. As a result, in the second half of the next memory cycle T3, the address AO of the area A of the pit map memory 20 operating in the read-modify-write cycle (read from the pit map memory 20 in the first half of the memory cycle T2 and stored in the latch 21) latched and later moved to RDR22) Address B
The contents of e are written through MLIX 25 and ALU 26 as shown by ■ in FIGS. 2 and 3.

In the above three memory cycles T1 to T3, swap processing for one word in areas A and B on the bitmap memory 20 (here, the content of address AO in area A and the content of address 8G in area B) is swapped. swap) is completed. As is clear, the swap processing (one swap cycle) in this embodiment reduces the processing time by one memory cycle compared to the conventional swap processing (see FIGS. 3 and 5). Now, when the above swap processing for one word (one swap cycle) is completed, bitbltllil
JI11 circuit 30 connects address generation circuit 27°28 to w4
Next address (here, address A of area A)
I, address 81) of area B, and move on to the next 1-word swap cycle.

The above explained the case of simple swap processing, but
Bitmap memory 20 output via latch 21
Read data in the area above (for example, area B) and other areas (for example, area B) held in the RD R22 in the previous memory cycle
For example, ALU2 performs calculations with the read data of area A).
6 and write the result in the above function area (area B). The above-described latch 21 is a circuit necessary for calculation between data read from the pit map memory 20 and calculation data such as mask data given via the system bus, and is also available in conventional bit map memory devices. has been done.

In addition, although the latch 21 was described as a transparent latch in the above embodiment, it is also possible to use a normal latch circuit. However, in this case, the read data from the bitmap memory 20 is
There is a possibility that high-speed transmission to 2B may not be possible. Further, the present invention can be applied to bitmap display devices, page printers, and even image processing devices as long as they are equipped with a bitmap memory device that requires swap processing.

[Effects of the Invention] As detailed above, according to the present invention, by performing a read-modify-write operation on the bitmap memory, data in the first area is read from the bitmap memory and temporarily held in the first half of the first memory cycle. Then, in the second half of the next memory cycle, write to the second area of the swap partner, read and temporarily hold the data in the second area in the first half of the same cycle, and then write to the first area in the second half of the next memory cycle. Therefore, one swap process can be performed in three memory cycles, and the swap process can be performed at high speed. Further, according to the present invention, there is no need to switch the data bus for each memory cycle during swap processing, so a switching circuit for this purpose is not required, and there is also only one temporary data holding means (- time data register) during swap processing. This simplifies the configuration. Furthermore, if a read data register for outputting read data to the outside is shared as the temporary data holding means, a dedicated temporary data holding means is not required.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a bitmap memory device according to an embodiment of the present invention, FIG. 2 is a diagram illustrating the flow of data during swap processing in the configuration of FIG. 1, and FIG. FIG. 4 is a timing chart explaining the operation of the bitmap memory during swap processing in the configuration shown in FIG.
The figure is a timing chart illustrating the operation of a bitmap memory during conventional swap processing. 20... Bit map memory, 21... Latch (first holding means), 22... Read data register (RD
R. second holding means), 25.29... multiplexer (
MUX), 27.28・7 Toss L/S generation circuit, 30-
t'footlock transfer (bitblt) control circuit. Applicant's agent Patent attorney Takehiko Suzue Figure 3

Claims (2)

[Claims] (1) A bitmap memory for storing figures, images, etc., a first holding means for holding data read from this bitmap memory, and a data held in the first holding means for external output or for the next memory cycle. a second holding means for holding data for write processing to the bitmap memory; and a first holding means for switching and outputting data held in the second holding means or external write data for writing processing to the bitmap memory. a multiplexer, first and second address generation circuits that generate addresses of first and second areas to be swapped on the bitmap memory, and a second multiplexer that switches outputs of the first and second address generation circuits. and a control means for repeatedly controlling swap processing of image data between the first and second areas in three cycles of first to third memory cycles by operating the bitmap memory in read-modify-write mode. , in the first and third memory cycles, the address from the first address generation circuit, and in the second memory cycle, the address from the second address generation circuit, respectively, as the address to the bitmap memory. A bitmap memory device comprising: control means for switching output from a second multiplexer. (2) The control means outputs write pulses to the bitmap memory in the second and third memory cycles, and refrains from outputting write pulses to the bitmap memory in the first memory cycle. A bitmap memory device according to claim 1, characterized in: