JPH01117329A - Manufacture of insulating film for thin film device - Google Patents

Manufacture of insulating film for thin film device

Info

Publication number
JPH01117329A
JPH01117329A JP27545987A JP27545987A JPH01117329A JP H01117329 A JPH01117329 A JP H01117329A JP 27545987 A JP27545987 A JP 27545987A JP 27545987 A JP27545987 A JP 27545987A JP H01117329 A JPH01117329 A JP H01117329A
Authority
JP
Japan
Prior art keywords
resist layer
insulating film
substrate
wiring pattern
wiring patterns
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP27545987A
Other languages
Japanese (ja)
Inventor
Kunio Omi
近江 邦夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP27545987A priority Critical patent/JPH01117329A/en
Publication of JPH01117329A publication Critical patent/JPH01117329A/en
Pending legal-status Critical Current

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  • Weting (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PURPOSE:To enable an insulating film in high flatness to be formed by a method wherein the second resist layer to be baked at the temperature lower than that in the first resist layer is formed on the first resist layer, and a metallic film is formed on a substrate and then the second resist layer is resolved to form wiring patterns, and the insulating film is formed on the wiring patterns and the first resist layer. CONSTITUTION:The second resist layer 12 is formed on the first resist layer 11 and then a metallic film 13 in almost the same thickness as that of the first resist layer 11 is formed on a substrate 10 including the second resist layer 12. Next, the substrate 10 is immersed in acetone to resolve the resist layer 12 of the substrate 10 so that the metallic film 13 may be lift off to form wiring patterns 14 comprising the first resist layer 11 and the metallic film 13 almost flatly on said substrate 10. Then, an interlayer insulating film 15 to be baked at the temperature lower than that the resist layer 11 is formed on the resist layer 11 and the wiring patterns while the other wiring patterns are successively formed in laminated layers on the insulating 15.

Description

【発明の詳細な説明】 [発明の目的] (産業上の利用分野) この発明は、例えば積層形薄膜コイル等の薄!!l装置
に係り、特にその絶縁膜製造方法に関する。
[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) This invention is applicable to thin film coils such as laminated thin film coils. ! The present invention relates to an insulating film manufacturing method for an insulating film manufacturing method.

(従来の技術) 一般に、alll装置を製造する場合は、複数の配線パ
ターンが順に積層構造に形成されるために、その配線パ
ターン間の平坦化の要請がある。これは、配線パターン
を積層構造に形成する際、下地となる層に段差があると
、配線パターンが断線したり、居間に短絡が発生するお
それがあるうえ、フォトリソグラフィ、あるいはエツチ
ング工程におけるパターン寸法が不均一となり、高密度
化が困難となるからである。また、配線パターンの層間
が平坦でない場合には、素子特性の低下を招き、特に、
磁気特性の低下により不具合が発生し易い磁気薄膜素子
にあっては、段差による磁気特性の低下が大きな問題と
なる。
(Prior Art) Generally, when manufacturing an all-in-one device, a plurality of wiring patterns are sequentially formed in a laminated structure, so there is a demand for flattening between the wiring patterns. This is because when forming a wiring pattern in a layered structure, if there is a step in the underlying layer, there is a risk that the wiring pattern will break or a short circuit will occur in the living room. This is because it becomes non-uniform, making it difficult to achieve high density. Furthermore, if the interlayers of the wiring pattern are not flat, the device characteristics will deteriorate, especially
In magnetic thin film elements that are prone to defects due to deterioration in magnetic properties, deterioration in magnetic properties due to differences in level poses a major problem.

このため、従来は、第2図に示す樹脂塗布法、第3図に
示すエッチパック法、第4図に示すバイアススパッタ法
等の手法により、層の平坦化が図られていた。
For this reason, layers have conventionally been flattened by techniques such as the resin coating method shown in FIG. 2, the etch pack method shown in FIG. 3, and the bias sputtering method shown in FIG. 4.

すなわち、第2図の樹脂塗布法は基板1a上に配線パタ
ーン2aを形成し、この配線パターン2aを含む基板1
a上にレジスト、ポリイミド等の熱硬化樹脂を塗布して
絶縁膜3aを形成することにより、その平坦化を図るも
のである。
That is, in the resin coating method shown in FIG. 2, a wiring pattern 2a is formed on a substrate 1a, and the substrate 1 including this wiring pattern 2a is
The planarization of the insulating film 3a is achieved by applying a resist or a thermosetting resin such as polyimide on the insulating film 3a.

第3図のエッチバック法は、配線パターン2bを形成し
た基板1b上にスパッタ等のドライプロセスで絶縁膜3
bを形成しく同図(a)参照)、さらに、この絶縁膜3
b上にレジスト4aを塗布して段差を緩和した後、同図
(b)に示すように、これら絶縁1m3bとレジスト4
aのエツチンググレードが等しくなるようにエツチング
して平坦に形成するもので、3amiconducto
rWorld  1984.1Orエッチバック法によ
る平坦化技術」に記載されるところのものである。
In the etch-back method shown in FIG. 3, an insulating film 3 is formed on a substrate 1b on which a wiring pattern 2b is formed by a dry process such as sputtering.
b (see figure (a)), and furthermore, this insulating film 3
After applying a resist 4a on the insulation layer 4a to reduce the level difference, as shown in FIG.
It is etched and formed flat so that the etching grade of a is the same, and 3amiconducto
rWorld 1984.1 "Planarization Technique by Or Etch-back Method".

第4図のバイアススパッタ法は、配線パターン2Cを形
成した基板1C上にスパッタにより絶縁m3cを形成す
る際に、ドライエツチングの効果が起こるように形成し
て平坦化を図るものである(同図(a)〜(C)参照)
The bias sputtering method shown in FIG. 4 is a method for flattening the insulation m3c by sputtering it on the substrate 1C on which the wiring pattern 2C is formed, by forming it so that a dry etching effect occurs (see FIG. 4). (See (a) to (C))
.

ところが、上記平坦化の手法では、いずれのものも、そ
の製造上、配線パターン2a、2b。
However, in all of the above flattening methods, the wiring patterns 2a and 2b are not uniform due to the manufacturing process.

2Cの密な箇所において、効果的に平坦化することがで
きるが、配線パターン2a、2b、2cの粗い箇所の平
坦化が困難であると共に、最外周層を効果的に平坦に形
成することが困難であった。
Although it is possible to effectively flatten the dense portions of the wiring patterns 2C, it is difficult to flatten the rough portions of the wiring patterns 2a, 2b, and 2c, and it is difficult to effectively form the outermost layer flat. It was difficult.

このため、製造上における信頼性及び素子特性の点で満
足いく製造が出来ず、特に、磁気薄膜素子を形成した場
合に磁気特性の低下を招くので、大きな問題となってい
た。
For this reason, manufacturing cannot be carried out satisfactorily in terms of manufacturing reliability and device characteristics, and in particular, when a magnetic thin film device is formed, the magnetic characteristics deteriorate, which is a big problem.

(発明が解決しようとする問題点) 以上述べたように、従来の平坦化の手法では、いずれの
ものも配線パターンの粗い箇所の平坦化が困難であると
共に、最外周層を効果的に平坦に形成することが困難な
ため、製造上における信頼性及び素子特性の点で満足い
く製造が出来ないものであった。
(Problems to be Solved by the Invention) As described above, with all conventional planarization methods, it is difficult to planarize rough areas of wiring patterns, and it is difficult to effectively planarize the outermost layer. Since it is difficult to form a semiconductor device, it has not been possible to manufacture the device satisfactorily in terms of manufacturing reliability and device characteristics.

この発明は上記の事情に鑑みてなされたもので、製作容
易にして、確実に平坦度の高い絶縁膜を形成し得るfi
ll装置の絶縁膜製造方法を提供することを目的とする
This invention was made in view of the above circumstances, and it is possible to easily manufacture and reliably form an insulating film with high flatness.
An object of the present invention is to provide a method for manufacturing an insulating film for a ll device.

[発明の構成] (問題点を解決するための手段) この発明は基板上に配線パターンに対応した第1のレジ
スト層を形成する第1の工程と、前記第1のレジスト層
上に該第1のレジスト層に比して低温で焼成される第2
のレジスト層を形成する第2の工程と、前記第2のレジ
スト層を含む基板上に前記第1のレジスト層に対応した
金属膜を形成する第3の工程と、前記第2のレジスト層
を溶解して前記金属膜で配線パターンを形成する第4の
工程と、前記配線パターン及び第1のレジスト層上に絶
縁膜を形成する第5の工程とを備えて薄膜装置を製造す
るようにしたものである。
[Structure of the Invention] (Means for Solving the Problems) The present invention includes a first step of forming a first resist layer corresponding to a wiring pattern on a substrate, and a step of forming a first resist layer on the first resist layer. The second resist layer is fired at a lower temperature than the first resist layer.
a second step of forming a resist layer; a third step of forming a metal film corresponding to the first resist layer on a substrate including the second resist layer; A thin film device is manufactured by including a fourth step of melting and forming a wiring pattern using the metal film, and a fifth step of forming an insulating film on the wiring pattern and the first resist layer. It is something.

(作用) 上記構成によれば、絶縁膜は略平坦に形成された第1の
レジスト層と配線パターン上に所望の平坦度を有して形
成することができる。これにより、配線パターンの粗密
と無関係に高精度な平坦度を有する絶縁膜を形成するこ
とが可能となり、可及的に製造工程における信頼性の向
上が図れ得ると共に、素子特性の低下の防止を図ること
ができる。
(Function) According to the above structure, the insulating film can be formed with desired flatness on the first resist layer and the wiring pattern which are formed substantially flat. This makes it possible to form an insulating film with highly accurate flatness regardless of the density of the wiring pattern, improving reliability in the manufacturing process as much as possible, and preventing deterioration of device characteristics. can be achieved.

(実施例) 以下、この発明の実施例について、図面を参照して詳細
に説明する。
(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

第1図はこの発明の一実施例に係るWJI!l装置の絶
縁膜製造方法を示すもので、先ず同図(a)に示すよう
に、基板10上には、先ず配線のネガパターンに対応し
て第1のレジスト層11が形成されて、例えば、180
°Cで焼成される。この第1のレジスト層11上には第
2のレジスト層12が形成されて、例えば100°Cで
焼成された後(同図(b)参照)、この第2のレジスト
層12を含む基板10上には蒸着あるいはスパッタ法に
よりA1.Au、Cu等の金属膜13が上記第1のレジ
スト層11と略同様の厚さ寸法だけ形成される(同図(
C)参照)。次に、基板1oが、例えば図示しないアセ
トンに浸漬される。これにより、基板10の第2のレジ
スト層12がアセトンにより溶解されて、その金属膜1
3がリフトオフされ、該基板10上には第1のレジスト
層11及び金属1!113で構成される配線パターン1
4が略平坦に形成される(同図(d)参照)。そして、
これら第1のレジスト層11及び配線パターン14上に
は上記第1のレジストH11より低温、例えば170°
Cで焼成される層間用の絶縁膜15が形成され(同図(
e)参照)、この絶縁膜15上には上述した工程で、積
層式に図示しない別の配線パターンが順に形成される。
FIG. 1 shows a WJI! according to an embodiment of the present invention! 1 shows a method for manufacturing an insulating film for an apparatus. As shown in FIG. , 180
Calcined at °C. A second resist layer 12 is formed on the first resist layer 11 and baked at, for example, 100°C (see FIG. A1. A metal film 13 made of Au, Cu, etc. is formed to have approximately the same thickness as the first resist layer 11 (see FIG.
See C). Next, the substrate 1o is immersed in, for example, acetone (not shown). As a result, the second resist layer 12 of the substrate 10 is dissolved by acetone, and the metal film 1
3 is lifted off, and a wiring pattern 1 composed of a first resist layer 11 and a metal 1!113 is formed on the substrate 10.
4 is formed substantially flat (see figure (d)). and,
On the first resist layer 11 and the wiring pattern 14, the temperature is lower than that of the first resist H11, for example, 170°.
An interlayer insulating film 15 is formed by baking with C (see FIG.
(see e)), another wiring pattern (not shown) is sequentially formed in a laminated manner on this insulating film 15 in the steps described above.

このように、上記薄膜装置の絶縁膜製造方法は配線のネ
ガパターンとなる第1のレジスト層11上に該第1のレ
ジスト層11に比して低温焼成される第2のレジスト1
112を形成して、その全面に第1のレジスト層11と
略同様の厚さ寸法を有した金属1113を形成した後、
その第2のレジスト層12を溶解して金属膜13をり゛
フトオフすることにより第1のレジスト層11と配線パ
ターン14を形成して、絶縁膜15を形成するように構
成した。これによれば、配線パターン14の粗密に係わ
ることなく、第1のレジスト層11と配線パターン14
を略平坦に形成することができるため、絶縁膜15を高
精度な平坦度を有して形成することが可能となり、可及
的に薄膜装置の製造工程における信頼性の向上が図り得
ると共に、所望の素子特性の確保が実現できる。これは
、磁気薄膜素子を形成する場合、磁気特性の低下を確実
に防止することができるため、特に有効な効果が期待で
きる。
As described above, the method for manufacturing an insulating film for a thin film device includes a second resist 1 which is fired at a lower temperature than the first resist layer 11 on the first resist layer 11 which becomes a negative pattern of wiring.
After forming a metal 1113 having substantially the same thickness as the first resist layer 11 on the entire surface thereof,
The second resist layer 12 was melted and the metal film 13 was lifted off to form the first resist layer 11 and the wiring pattern 14, thereby forming the insulating film 15. According to this, the first resist layer 11 and the wiring pattern 14 can be separated without regard to the density of the wiring pattern 14.
Since the insulating film 15 can be formed substantially flat, it is possible to form the insulating film 15 with highly accurate flatness, and the reliability in the manufacturing process of the thin film device can be improved as much as possible. Desired device characteristics can be ensured. This can be expected to have a particularly effective effect when forming a magnetic thin film element, since deterioration of magnetic properties can be reliably prevented.

なお、この発明は上記実施例に限ることなく、その他、
この発明の要旨を逸脱しない範囲で種々の変形を実施し
得ることは勿論のことである。
Note that this invention is not limited to the above embodiments, but also includes
It goes without saying that various modifications can be made without departing from the spirit of the invention.

[発明の効果] 以上詳述したように、この発明によれば、製作容易にC
て、確実に平坦度の高い絶縁膜を形成し得る薄膜装置の
絶縁+m製造方法を提供することができる。
[Effect of the invention] As detailed above, according to the present invention, C.
Thus, it is possible to provide an insulation+m manufacturing method for a thin film device that can reliably form an insulating film with high flatness.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明の一実施例に係る薄膜装置の絶縁膜製
造方法を説明するために示した図、第2図乃至第4図は
それぞれ従来の薄膜装置の絶縁膜製造方法を説明するた
めに示した図である。 10・・・基板、11・・・第1のレジスト層、12・
・・第2のレジスト層、13・・・金属膜、14・・・
配線パターン、15・・・絶縁膜。 出願人代理人  弁理士 鈴江武彦 (b) (c) 払 (d) (e) 第1図 52rjA (a) (b) 第3図 (a) −(b) (C) 第4rxJ
FIG. 1 is a diagram for explaining an insulating film manufacturing method for a thin film device according to an embodiment of the present invention, and FIGS. 2 to 4 are diagrams for explaining a conventional method for manufacturing an insulating film for a thin film device, respectively. FIG. DESCRIPTION OF SYMBOLS 10... Substrate, 11... First resist layer, 12...
...Second resist layer, 13...Metal film, 14...
Wiring pattern, 15...insulating film. Applicant's agent Patent attorney Takehiko Suzue (b) (c) Payment (d) (e) Figure 1 52rjA (a) (b) Figure 3 (a) - (b) (C) No. 4rxJ

Claims (1)

【特許請求の範囲】[Claims]  基板上に配線パターンに対応した第1のレジスト層を
形成する第1の工程と、前記第1のレジスト層上に該第
1のレジスト層に比して低温で焼成される第2のレジス
ト層を形成する第2の工程と、前記第2のレジスト層を
含む基板上に前記第1のレジスト層に対応した金属膜を
形成する第3の工程と、前記第2のレジスト層を溶解し
て前記金属膜で配線パターンを形成する第4の工程と、
前記配線パターン及び第1のレジスト層上に絶縁膜を形
成する第5の工程とを具備したことを特徴とする薄膜装
置の絶縁膜製造方法。
a first step of forming a first resist layer corresponding to a wiring pattern on a substrate; and a second resist layer baked at a lower temperature than the first resist layer on the first resist layer. a second step of forming a metal film corresponding to the first resist layer on the substrate including the second resist layer; and a third step of dissolving the second resist layer. a fourth step of forming a wiring pattern with the metal film;
A method for manufacturing an insulating film for a thin film device, comprising a fifth step of forming an insulating film on the wiring pattern and the first resist layer.
JP27545987A 1987-10-30 1987-10-30 Manufacture of insulating film for thin film device Pending JPH01117329A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27545987A JPH01117329A (en) 1987-10-30 1987-10-30 Manufacture of insulating film for thin film device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27545987A JPH01117329A (en) 1987-10-30 1987-10-30 Manufacture of insulating film for thin film device

Publications (1)

Publication Number Publication Date
JPH01117329A true JPH01117329A (en) 1989-05-10

Family

ID=17555825

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27545987A Pending JPH01117329A (en) 1987-10-30 1987-10-30 Manufacture of insulating film for thin film device

Country Status (1)

Country Link
JP (1) JPH01117329A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20160120906A (en) * 2015-04-09 2016-10-19 (주)인터플렉스 The method of sputtering

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20160120906A (en) * 2015-04-09 2016-10-19 (주)인터플렉스 The method of sputtering

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