JPH01111349A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH01111349A JPH01111349A JP27081587A JP27081587A JPH01111349A JP H01111349 A JPH01111349 A JP H01111349A JP 27081587 A JP27081587 A JP 27081587A JP 27081587 A JP27081587 A JP 27081587A JP H01111349 A JPH01111349 A JP H01111349A
- Authority
- JP
- Japan
- Prior art keywords
- reference voltage
- logic circuit
- voltage line
- cell
- basic cell
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 11
- 239000003990 capacitor Substances 0.000 abstract description 7
- 238000000034 method Methods 0.000 abstract description 5
- 238000010586 diagram Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 2
- 230000000087 stabilizing effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11801—Masterslice integrated circuits using bipolar technology
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特に複数の基本セルを配列
した構造を有する大規模マスタースライス型の半導体装
置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a large-scale master slice type semiconductor device having a structure in which a plurality of basic cells are arranged.
従来、この種の半導体装置は、第３図に示すように、チ
ップ１の中にｍ（ｍ≧２の整数）個の基本セル２−１〜
２−ｉ−ｍ（２≦ｉ≦ｍの整数）から成るｎ（ｎ≧の整
数）列の基本セル列３−１〜Ｂ−ｊ〜３−ｎ（２≦ｊ≦
ｎの整数）を形成し、それぞれの基本セル列３−１〜３
−ｊ〜３−ｎにそれぞれの基本セル２−１〜２−ｉ〜２
−ｍに共通に接続できる基準電圧線４を並列に形成した
構成になっている。Conventionally, this type of semiconductor device has m (an integer of m≧2) basic cells 2-1 to 2-1 in a chip 1, as shown in FIG.
Basic cell strings 3-1 to B-j to 3-n (2≦j≦
n integer), and each basic cell column 3-1 to 3
-j to 3-n each basic cell 2-1 to 2-i to 2
The configuration is such that reference voltage lines 4 that can be commonly connected to -m are formed in parallel.
それぞれの基本セル２−ｉは、第４図に示すように、３
個のＮＰＮ型のトランジスタと３個の抵抗とを有し配線
工程によって結線することによって論理回路を形成する
。Each basic cell 2-i has 3 cells as shown in FIG.
A logic circuit is formed by connecting NPN transistors and three resistors through a wiring process.
いま、第５図に示すように、基本セル２−ｉが回路とし
て使用され基本セル２−（ｉ＋１）が回路として使用さ
れないとすると、基本セル２−ｉは配線工程によって結
線され基準電圧線４に接続されて論理回路２ａを形成す
る。しがし、基本セル２−（ｉ＋１）は配線が行われず
、基準電圧線４にも接続されない。Now, as shown in FIG. 5, assuming that basic cell 2-i is used as a circuit and basic cell 2-(i+1) is not used as a circuit, basic cell 2-i is connected by the wiring process and connected to reference voltage line 4. is connected to form a logic circuit 2a. However, basic cell 2-(i+1) is not wired and is not connected to reference voltage line 4 either.
上述した従来の半導体装置は、基本セルと基準電圧線と
の接続を論理回路として使用される基本セルのみに行い
、論理回路として使用されない基本セルには全く接続し
ないようになっているので、使用されない基本セルは全
くむだになるという欠点がある。In the conventional semiconductor device described above, the basic cells and reference voltage lines are connected only to the basic cells that are used as logic circuits, and are not connected at all to basic cells that are not used as logic circuits. The disadvantage is that basic cells that are not used are completely wasted.
本発明は、複数のトランジスタを有する基本セルを複数
配列した複数列の基本セル列と、それぞれの前記基本セ
ルに共通に接続可能な基準電圧線とを有する半導体装置
において、前記基本セルのうち論理回路として未使用の
基本セルのトランジスタを接地端子と前記基準電圧線と
の間に挿入するよう形成される配線を有している。The present invention provides a semiconductor device having a plurality of basic cell rows in which a plurality of basic cells each having a plurality of transistors are arranged, and a reference voltage line that can be commonly connected to each of the basic cells. It has a wiring formed to insert a transistor of a basic cell that is not used as a circuit between a ground terminal and the reference voltage line.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の第１の実施例を用いる基本セルの結線
図である。FIG. 1 is a wiring diagram of a basic cell using a first embodiment of the present invention.
第１図に示すように、基本セル列中の基本セル２−ｉが
論理回路として使用され、基本セル２−（ｉ−１＞が論
理回路として使用されない場合、基本セル２−ｉは配線
工程によって内部が論理的・ 動作を行うように結線さ
れ、更に、基準電圧線４と接続することによって基準電
圧が供給されて論理回路２ａとなる。As shown in FIG. 1, when the basic cell 2-i in the basic cell row is used as a logic circuit and the basic cell 2-(i-1> is not used as a logic circuit, the basic cell 2-i is used in the wiring process. The internal circuit is connected to perform logical operations, and is further connected to a reference voltage line 4 to be supplied with a reference voltage, forming a logic circuit 2a.
一方、基本セル２−（ｉ＋１）は論理回路として使用さ
れないため、基本セル２−ｉのような論理回路的な構成
をとらず、各ＮＰＮ型のトランジスタのコレクタとエミ
ッタは接地端子へ接続され、ベースは基準電圧線４に接
続されている。On the other hand, since basic cell 2-(i+1) is not used as a logic circuit, it does not have a logic circuit-like configuration like basic cell 2-i, and the collector and emitter of each NPN type transistor are connected to the ground terminal. The base is connected to a reference voltage line 4.
論理回路として使用しない基本セルを配線工程によって
上記のように配線を形成することによって、各トランジ
スタは接地端子と基準電圧線との間で、第１図に破線で
示すように、コンデンサ２ｂとして作用する。従って、
論理回路として使用されない基本セルはすべて接地端子
と基準電圧線との間に接続される並列コンデンサとなる
。By forming the wiring in the basic cells that are not used as a logic circuit in the wiring process as described above, each transistor acts as a capacitor 2b between the ground terminal and the reference voltage line, as shown by the broken line in FIG. do. Therefore,
All basic cells not used as logic circuits become parallel capacitors connected between the ground terminal and the reference voltage line.
第２図は本発明の第２の実施例に用いる基本セルの結線
図である。FIG. 2 is a wiring diagram of a basic cell used in a second embodiment of the present invention.
第２図に示すように、第２の実施例に用いる基本セルで
は、論理回路として使用されていない基本セル２−（ｉ
＋１＞はトラジスタの接続方法が直列接続となっている
。この場合も、基本セル２−（ｉ＋１＞は、第２図に破
線で示すように、基準電圧線４と接地端子との間に挿入
されたコンデンｖ２゜とじて動作する。As shown in FIG. 2, in the basic cell used in the second embodiment, basic cell 2-(i
+1>, the transistors are connected in series. In this case as well, the basic cell 2-(i+1> operates as a capacitor v2° inserted between the reference voltage line 4 and the ground terminal, as shown by the broken line in FIG. 2.
以上説明したように本発明は、論理回路として使用しな
い基本セルのトランジスタを基準電圧線と接地端子との
間に挿入して基準電圧線に対するバイパスコンデンサと
して使用することにより、基準電圧線のインピーダンス
を低下させてノイズに影響されない一定の基準電圧を供
給することができるので、半導体装置の論理動作を安定
化する効果がある。As explained above, the present invention reduces the impedance of the reference voltage line by inserting a transistor of a basic cell that is not used as a logic circuit between the reference voltage line and the ground terminal and using it as a bypass capacitor for the reference voltage line. Since it is possible to lower the reference voltage and supply a constant reference voltage that is not affected by noise, it has the effect of stabilizing the logic operation of the semiconductor device.
第１図は本発明の第１の実施例に用いる基本セルの結線
図、第２図は本発明の第２の実施例に用いる基本セルの
結線図、第３図はマスタースライス型の半導体装置のチ
ップの一例の平面図、第４図は第３図の基本セルの内部
素子の配置図、第５図は従来の半導体装置の一例に用い
る基本セルの結線図である。
１・・・チップ、２−１〜２−ｉ〜２−ｍ・・・基本セ
ル、２＠・・・論理回路、２ｈ 、２ｅ・・・コンｆ７
す、−３−１〜３−ｊ〜３−ｎ・・・基本セル列、４・
・・基準電圧線。Fig. 1 is a wiring diagram of a basic cell used in a first embodiment of the present invention, Fig. 2 is a wiring diagram of a basic cell used in a second embodiment of the invention, and Fig. 3 is a master slice type semiconductor device. 4 is a plan view of an example of a chip, FIG. 4 is a layout diagram of internal elements of the basic cell of FIG. 3, and FIG. 5 is a wiring diagram of a basic cell used in an example of a conventional semiconductor device. 1...Chip, 2-1~2-i~2-m...Basic cell, 2@...Logic circuit, 2h, 2e...Conf7
-3-1 to 3-j to 3-n...Basic cell row, 4.
...Reference voltage line.
Claims (1)
複数列の基本セル列と、それぞれの前記基本セルに共通
に接続可能な基準電圧線とを有する半導体装置において
、前記基本セルのうち論理回路として未使用の基本セル
のトランジスタを接地端子と前記基準電圧線との間に挿
入するよう形成される配線を有することを特徴とする半
導体装置。In a semiconductor device having a plurality of basic cell rows in which a plurality of basic cells each having a plurality of transistors are arranged, and a reference voltage line that can be commonly connected to each of the basic cells, one of the basic cells that is not used as a logic circuit. A semiconductor device comprising a wiring formed to insert a transistor of a basic cell between a ground terminal and the reference voltage line.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27081587A JPH01111349A (en) | 1987-10-26 | 1987-10-26 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27081587A JPH01111349A (en) | 1987-10-26 | 1987-10-26 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01111349A true JPH01111349A (en) | 1989-04-28 |
Family
ID=17491405
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27081587A Pending JPH01111349A (en) | 1987-10-26 | 1987-10-26 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01111349A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05275661A (en) * | 1992-03-30 | 1993-10-22 | Nec Corp | Semiconductor device |
-
1987
- 1987-10-26 JP JP27081587A patent/JPH01111349A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05275661A (en) * | 1992-03-30 | 1993-10-22 | Nec Corp | Semiconductor device |
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