JPH01109735A - Inspection method of wiring layer - Google Patents
Inspection method of wiring layerInfo
- Publication number
- JPH01109735A JPH01109735A JP26711487A JP26711487A JPH01109735A JP H01109735 A JPH01109735 A JP H01109735A JP 26711487 A JP26711487 A JP 26711487A JP 26711487 A JP26711487 A JP 26711487A JP H01109735 A JPH01109735 A JP H01109735A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- wiring layer
- layer
- light
- infrared light
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 14
- 238000007689 inspection Methods 0.000 title 1
- 239000000758 substrate Substances 0.000 claims abstract description 45
- 239000004065 semiconductor Substances 0.000 claims abstract description 14
- 239000010410 layer Substances 0.000 abstract description 44
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 8
- 230000002950 deficient Effects 0.000 abstract description 8
- 239000011248 coating agent Substances 0.000 abstract description 7
- 238000000576 coating method Methods 0.000 abstract description 7
- 239000011229 interlayer Substances 0.000 abstract description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 5
- 229910052681 coesite Inorganic materials 0.000 abstract description 4
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 4
- 239000000377 silicon dioxide Substances 0.000 abstract description 4
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 4
- 229910052682 stishovite Inorganic materials 0.000 abstract description 4
- 229910052905 tridymite Inorganic materials 0.000 abstract description 4
- 239000005360 phosphosilicate glass Substances 0.000 description 15
- 238000003384 imaging method Methods 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- 239000010408 film Substances 0.000 description 6
- 238000002834 transmittance Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000012805 post-processing Methods 0.000 description 2
- ZCYVEMRRCGMTRW-UHFFFAOYSA-N 7553-56-2 Chemical compound [I] ZCYVEMRRCGMTRW-UHFFFAOYSA-N 0.000 description 1
- 229910000661 Mercury cadmium telluride Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000000295 emission spectrum Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910052740 iodine Inorganic materials 0.000 description 1
- 239000011630 iodine Substances 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000012958 reprocessing Methods 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
半導体基板上に形成された配線層の被覆状態を検査する
方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a method for inspecting the covering state of a wiring layer formed on a semiconductor substrate.
迅速に、金属配線層の被覆状態の良否を判定し。Quickly determines whether the coating state of the metal wiring layer is good or bad.
不良基板を除去するか、または再処理することを目的と
し。The purpose is to remove or reprocess defective boards.
半導体基板上に配線層を形成後、該基板の裏面より波長
1.3〜6μmの赤外光を含む光を照射し。After forming a wiring layer on a semiconductor substrate, light containing infrared light with a wavelength of 1.3 to 6 μm is irradiated from the back surface of the substrate.
該基板を透過する光を赤外検出器で検出し、透過光によ
り該配線層の被覆状態を検査するように構成する。The configuration is such that the light transmitted through the substrate is detected by an infrared detector, and the covering state of the wiring layer is inspected using the transmitted light.
本発明は半導体基板上に形成された配線層の被覆状態を
検査する方法に関する。The present invention relates to a method for inspecting the covering state of a wiring layer formed on a semiconductor substrate.
第3図はコンタクトホールの段差被覆を説明する基板断
面図である。FIG. 3 is a cross-sectional view of the substrate illustrating the step covering of the contact hole.
図において、lはSi基板、2はフィールドSiO□層
、3はゲートSiO□層、4はゲートポリSi層、5は
PSG層間絶縁層36はコンタクトホール、7はAI配
線層である。In the figure, 1 is a Si substrate, 2 is a field SiO□ layer, 3 is a gate SiO□ layer, 4 is a gate poly-Si layer, 5 is a PSG interlayer insulating layer 36 is a contact hole, and 7 is an AI wiring layer.
第4図は配線交、差部の段差被覆を説明する基板断面図
である。FIG. 4 is a cross-sectional view of the substrate illustrating wiring intersection and step covering of the difference portion.
図において、1はSi基板、7は下層AI配線層。In the figure, 1 is a Si substrate, and 7 is a lower AI wiring layer.
8はPSG層間絶縁層、9は上層AI配線層である。8 is a PSG interlayer insulating layer, and 9 is an upper AI wiring layer.
集積回路のウェハプロセスにおいて、第3図に示される
ように電極引き出し用コンタクトホール6上(A部)や
、第4図のように2本の配線7゜9が絶縁層を介して交
差する部分(B部)で、配線層の被覆が薄くなり、甚だ
しい場合は断線を生ずることがある。In the wafer process of integrated circuits, as shown in Fig. 3, above the contact hole 6 for leading out the electrode (part A), and as shown in Fig. 4, the part where two wires 7°9 intersect with each other through an insulating layer. (Part B), the coating of the wiring layer becomes thin, and in severe cases, disconnection may occur.
このような段差被覆を改善する方法として、眉間絶縁層
に燐珪酸ガラス(PSG)を用い、これをリフローする
方法が用いられている。As a method for improving such step coverage, a method is used in which phosphosilicate glass (PSG) is used for the glabella insulating layer and reflowed.
この方法はPSGを基板上に堆積し、第3図の場合はコ
ンタクトホールの窓開けをした後、 1050℃以上に
加熱すると、 PSGは流動し、コンタクトホールの急
峻な段差をなだらかにする。In this method, PSG is deposited on a substrate, and in the case of Fig. 3, after opening a contact hole, the PSG is heated to 1050° C. or above, and then the PSG flows and smooths out the steep steps of the contact hole.
しかし、この方法ではデバイスの微細化が進んで、コン
タクトホールの直径が0.5μm程度になると、流動に
より孔が塞がってしまうという問題がある。However, this method has a problem in that as devices become smaller and the diameter of the contact hole becomes approximately 0.5 μm, the hole becomes clogged due to flow.
また、微細化に伴ってプロセスの低温化が必要になり、
1oso℃以上に加熱ができなくなってきている。In addition, as miniaturization requires lowering the process temperature,
It has become impossible to heat the temperature above 1 oso℃.
さらに第4図の場合は下層配線がAIであるため。Furthermore, in the case of FIG. 4, the lower layer wiring is AI.
上層配線の段差被覆改善のためのPSGのリフローは困
難である。これはAIは500℃程度でPSG 、或い
は5iO1と激しく反応して、下層配線に障害を生ずる
ためである。It is difficult to reflow PSG to improve step coverage of upper layer wiring. This is because AI reacts violently with PSG or 5iO1 at about 500° C., causing damage to the underlying wiring.
一方、リフロー温度を下げるため、Pbを含ませたSi
O□や、燐濃度を増やしたPSGが用いられることもあ
るが、これらのものは吸湿性が増し、集積回路の特性を
劣化させる原因になる。On the other hand, in order to lower the reflow temperature, Si containing Pb
O□ or PSG with increased phosphorus concentration is sometimes used, but these increase hygroscopicity and cause deterioration of the characteristics of the integrated circuit.
また1段差被覆の改善に、エツチングにより段差に丸み
を持たせる方法がある。しかし、その制御は非常に不安
定なものである。Another method for improving the one-level difference coating is to make the level difference rounded by etching. However, the control is extremely unstable.
しかしながら1以上述べた種々の段差被覆改善方法は、
すべての製造ロフトにわたって完全無欠にすることは極
めて困難である。However, the various step coverage improvement methods mentioned above are
It is extremely difficult to achieve perfection across all manufacturing lofts.
そこで1本発明は、金属配線層を基板上に堆積直後に9
段差被覆の不良個所を検出し、エツチングや堆積のプロ
セスを再度行って不良基板を修正するか、或いは不良基
板に対して後工程が行われる損失を避けることを目的と
する。Therefore, one aspect of the present invention is to deposit the metal wiring layer on the substrate at 90°C immediately after depositing the metal wiring layer on the substrate.
The purpose is to detect a defective part of the step coating and repair the defective substrate by repeating the etching or deposition process, or to avoid the loss of post-processing performed on the defective substrate.
上記問題点の解決は、半導体基板上に配線層を形成後、
該基板の裏面より波長1.3〜6μmの赤外光を含む光
を照射し、該基板を透過する光を赤外検出器で検出し、
透過光により該配線層の被覆状態を検査する方法により
達成される。The solution to the above problem is to form a wiring layer on a semiconductor substrate, then
irradiating light containing infrared light with a wavelength of 1.3 to 6 μm from the back side of the substrate, detecting the light transmitted through the substrate with an infrared detector,
This is achieved by a method of inspecting the coating state of the wiring layer using transmitted light.
第1図は本発明を説明する半導体基板の断面図である。 FIG. 1 is a cross-sectional view of a semiconductor substrate for explaining the present invention.
図において、1はSt基板、2はフィールド5i(h層
、3はゲートSiO□層、4はゲートポリSi層、5は
PSG層間絶縁層、6はコンタクトホール、7は^l配
線層である。In the figure, 1 is an St substrate, 2 is a field 5i (h layer, 3 is a gate SiO□ layer, 4 is a gate poly-Si layer, 5 is a PSG interlayer insulating layer, 6 is a contact hole, and 7 is a ^l wiring layer).
本発明は、^1配線層7を基板の表面側全面に堆積後、
その配線層のパターニング前にSt基板lの裏面より赤
外光(IR)を照射し、矢印で示される漏洩赤外光を検
出して断線の有無を判定するものである。In the present invention, after depositing the ^1 wiring layer 7 on the entire surface side of the substrate,
Before patterning the wiring layer, infrared light (IR) is irradiated from the back surface of the St substrate 1, and leaked infrared light indicated by an arrow is detected to determine whether there is a disconnection.
ここで、赤外光は波長1.3〜6μmを含むものを用い
ると、 St、 Sing、 PSG等はこの波長範囲
の赤外光はよく透過し、^lはどの波長の赤外光も透過
しない。Here, when using infrared light with a wavelength of 1.3 to 6 μm, St, Sing, PSG, etc. can easily transmit infrared light in this wavelength range, and ^l can transmit infrared light of any wavelength. do not.
一般に、半導体装置は配線金属以外は単結晶および多結
晶Siと、 CVD−PSGや、 CCVD−5inや
、熱酸化SiO2のような主成分がSingからなる膜
よりなっている。In general, semiconductor devices are made of single-crystal and polycrystalline Si, and films whose main component is Sing, such as CVD-PSG, CCVD-5in, and thermally oxidized SiO2, except for wiring metals.
これに対して、Siの透過率は波長が1.3μm付近で
大きく変化し1.3μm以上で増加し、一方SiO□の
透過率は6μm以上で大きく減少する。On the other hand, the transmittance of Si changes significantly when the wavelength is around 1.3 μm and increases when the wavelength is 1.3 μm or more, while the transmittance of SiO□ decreases significantly when the wavelength is 6 μm or more.
透過率を測定した一例をあげると1次のようである。An example of measured transmittance is first order.
波長(μm) 1 1.5〜4 10透過率
Si 0.2 99 70(%) 5
iOz 90 90 3PSG
90 90 3AI O,00,
00,0
但し、膜厚は、 St : 300 、5iOt :
70. PSG:300゜At : 1 μm である
。Wavelength (μm) 1 1.5~4 10 Transmittance
Si 0.2 99 70(%) 5
iOz 90 90 3PSG
90 90 3AI O,00,
00,0 However, the film thickness is St: 300, 5iOt:
70. PSG: 300°At: 1 μm.
上表より、 Stの厚さが300μm、 5t(hの厚
さが高々10μmの半導体装置であれば、波長1.5〜
4μmの赤外光は金属膜がなければ90%以上が透過し
、 1μmのAt膜があると透過率はo、0%となるこ
とが分かる。From the above table, if the thickness of St is 300 μm and the thickness of 5T (h is at most 10 μm), the wavelength is 1.5~
It can be seen that more than 90% of infrared light of 4 μm is transmitted if there is no metal film, and if there is an At film of 1 μm, the transmittance becomes o, 0%.
上記の測定結果は、1.5〜4μmの波長範囲で行った
が、上述の理由により1.3〜6μmの波長範囲でも時
開等に近い効果がある。Although the above measurement results were carried out in the wavelength range of 1.5 to 4 μm, for the above-mentioned reasons, even in the wavelength range of 1.3 to 6 μm, there is an effect similar to that of time opening.
第2図は本発明の一実施例を説明する装置の構成図であ
る。FIG. 2 is a configuration diagram of an apparatus for explaining an embodiment of the present invention.
7 図において、ランプハウス11より出た赤外光はミ
ラー12で反射して半導体基板13の裏面に入射される
。7, infrared light emitted from a lamp house 11 is reflected by a mirror 12 and is incident on the back surface of a semiconductor substrate 13.
半導体基板13を透過した光は結像レンズ14により結
像面15上に結像され、結像面15に置かれた赤外検出
器16により検出されアンプ17で増幅して出力される
。The light transmitted through the semiconductor substrate 13 is imaged on an imaging plane 15 by an imaging lens 14, detected by an infrared detector 16 placed on the imaging plane 15, amplified by an amplifier 17, and output.
また1図示していないが基板13と結像レンズ14の間
にチョッパをおいて、赤外検出器16の出力を交流増幅
することもできる。Although not shown, a chopper may be placed between the substrate 13 and the imaging lens 14 to AC amplify the output of the infrared detector 16.
この場合、基板表面全域を結像レンズ14で縮小して赤
外検出器16の感光板上に結像させる。In this case, the entire surface of the substrate is reduced by the imaging lens 14 and an image is formed on the photosensitive plate of the infrared detector 16.
ランプハウス11より出る赤外光は1.3〜6μmの波
長範囲内の特定の波長の単色光であってもよく、またこ
の範囲内の複数の単色光であってもよい。さらに、この
範囲内の光取外の赤外、可視。The infrared light emitted from the lamp house 11 may be monochromatic light with a specific wavelength within the wavelength range of 1.3 to 6 μm, or may be a plurality of monochromatic lights within this range. Additionally, light within this range can be removed from the infrared and visible.
紫外光が含まれていても、これらの光は金属膜を透過で
きないので9本発明を実施する上で障害となることはな
い。Even if ultraviolet light is included, this light will not impede the implementation of the present invention because it cannot pass through the metal film.
ランプハウス11は1例えば沃素(I)を封入したタン
グステンランプを用いる。この場合の発光スペクトルは
、波長が0.2μm以上になると立ち上がり1μm近傍
でピークになり、波長の増加ととに漸減する連続スペク
トルである。The lamp house 11 uses, for example, a tungsten lamp filled with iodine (I). The emission spectrum in this case is a continuous spectrum that rises when the wavelength becomes 0.2 μm or more, reaches a peak near 1 μm, and gradually decreases as the wavelength increases.
赤外検出器16は、 HgCdTe系の化合物半導体を
用いた光起電力素子、またはpbs薄膜をガラス基板に
被着した光伝導素子を用いる。The infrared detector 16 uses a photovoltaic element using an HgCdTe-based compound semiconductor or a photoconductive element in which a PBS thin film is adhered to a glass substrate.
いま、赤外検出器16の素子を1個使用した場合は、^
l膜のカバレージの悪い場所の数、あるいは悪さの程度
に応じてアンプ17の出力電圧がアナログに変化する。Now, if one element of the infrared detector 16 is used, ^
The output voltage of the amplifier 17 changes in an analog manner depending on the number or degree of poor coverage of the film.
一方、赤外検出器16の素子を多数アレイ状に並べたも
のを用いれば、結像面15には基板13の像が得られる
ので、アンプ17の出力をコンピュータ処理して基板1
3のどの場所がカバレージ不良であるかをマツプ化する
こともできる。On the other hand, if a large number of elements of the infrared detector 16 are arranged in an array, an image of the substrate 13 can be obtained on the imaging plane 15, so the output of the amplifier 17 is processed by a computer to
It is also possible to map which locations in 3 have poor coverage.
以上詳細に説明したように本発明によれば、迅速に、金
属配線層の被覆状態の良否を判定することができる。As described in detail above, according to the present invention, it is possible to quickly determine whether the covering state of a metal wiring layer is good or bad.
従って、不良基板を除去することにより、後工程を行う
ことによる損失を除き、または不良基板を再処理するこ
とにより良品基板に変えることができる。Therefore, by removing the defective substrate, losses due to post-processing can be eliminated, or by reprocessing the defective substrate, it is possible to convert it into a good substrate.
第1図は本発明を説明する半導体基板の断面図。
第2図は本発明の一実施例を説明する装置の構成図。
第3図はコンタクトホールの段差被覆を説明する基板断
面図。
第4図は配線交差部の段差被覆を説明する基板断面図で
ある。
図において。
1はSi基板。
2はフィールドSiO□層。
3はゲートSin、層。
4はゲートポリSi層。
5はPSG層間絶縁層。
6はコンタクトホール。
7はAI配線層。
11はランプハウス。
12はミラー。
13は半導体基板。
14は結像レンズ。
15は結像面。
16は赤外検出器。
矛2MFIG. 1 is a cross-sectional view of a semiconductor substrate explaining the present invention. FIG. 2 is a configuration diagram of an apparatus for explaining an embodiment of the present invention. FIG. 3 is a cross-sectional view of the substrate illustrating the step covering of the contact hole. FIG. 4 is a cross-sectional view of the substrate illustrating step coverage at wiring intersections. In fig. 1 is a Si substrate. 2 is a field SiO□ layer. 3 is the gate Sin layer. 4 is a gate poly-Si layer. 5 is a PSG interlayer insulating layer. 6 is a contact hole. 7 is the AI wiring layer. 11 is the lamp house. 12 is a mirror. 13 is a semiconductor substrate. 14 is an imaging lens. 15 is an imaging plane. 16 is an infrared detector. Spear 2M
Claims (1)
長1.3〜6μmの赤外光を含む光を照射し、該基板を
透過する光を赤外検出器で検出し、透過光により該配線
層の被覆状態を検査することを特徴とする配線層の検査
方法。After forming a wiring layer on a semiconductor substrate, light containing infrared light with a wavelength of 1.3 to 6 μm is irradiated from the back side of the substrate, and the light transmitted through the substrate is detected by an infrared detector. A method for inspecting a wiring layer, comprising inspecting a covering state of the wiring layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP26711487A JPH0687478B2 (en) | 1987-10-22 | 1987-10-22 | Wiring layer inspection method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP26711487A JPH0687478B2 (en) | 1987-10-22 | 1987-10-22 | Wiring layer inspection method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH01109735A true JPH01109735A (en) | 1989-04-26 |
JPH0687478B2 JPH0687478B2 (en) | 1994-11-02 |
Family
ID=17440258
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP26711487A Expired - Lifetime JPH0687478B2 (en) | 1987-10-22 | 1987-10-22 | Wiring layer inspection method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0687478B2 (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0635883A2 (en) * | 1993-07-19 | 1995-01-25 | Hamamatsu Photonics K.K. | Semiconductor device inspection system |
EP0653626A1 (en) * | 1993-11-16 | 1995-05-17 | Hamamatsu Photonics K.K. | Semiconductor device inspection system |
US6002792A (en) * | 1993-11-16 | 1999-12-14 | Hamamatsu Photonics Kk | Semiconductor device inspection system |
JP2002083265A (en) * | 2000-09-05 | 2002-03-22 | Nidek Co Ltd | Character recognition device for semiconductor wafer, and character recognizing optical unit |
-
1987
- 1987-10-22 JP JP26711487A patent/JPH0687478B2/en not_active Expired - Lifetime
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0635883A2 (en) * | 1993-07-19 | 1995-01-25 | Hamamatsu Photonics K.K. | Semiconductor device inspection system |
EP0635883A3 (en) * | 1993-07-19 | 1995-09-20 | Hamamatsu Photonics Kk | Semiconductor device inspection system. |
US5532607A (en) * | 1993-07-19 | 1996-07-02 | Hamamatsu Photonics K.K. | Semiconductor device inspection system involving superimposition of image data for detecting flaws in the semiconductor device |
EP0653626A1 (en) * | 1993-11-16 | 1995-05-17 | Hamamatsu Photonics K.K. | Semiconductor device inspection system |
US6002792A (en) * | 1993-11-16 | 1999-12-14 | Hamamatsu Photonics Kk | Semiconductor device inspection system |
JP2002083265A (en) * | 2000-09-05 | 2002-03-22 | Nidek Co Ltd | Character recognition device for semiconductor wafer, and character recognizing optical unit |
Also Published As
Publication number | Publication date |
---|---|
JPH0687478B2 (en) | 1994-11-02 |
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