JPH01103868A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To speed up an element by a method wherein a second compensatory base region, lower in impurity concentration that a first compensatory base region and higher in impurity concentration than a base region, is formed between the first compensatory base region and an emitter region. CONSTITUTION:Between a P<+>-type first compensatory base region 6 and an emitter region 10, a P-type second compensatory base region 9 is formed, reducing base resistance between the first compensatory base region 6 and the emitter region 10 and enabling an element to operate at higher speeds. With the second compensatory base region 9 being lower in impurity concentration than the first compensatory base region 6, reduction is small in emitter.base junction breakdown strength in the presence of contact of the second compensatory base region 9 with the emitter region 10. This design does not increase the collector.base capacity.

Description

DETAILED DESCRIPTION OF THE INVENTION Conventionally, in this type of bipolar transistor, as shown in FIG. Alternatively, as shown in FIG. 5, the emitter region 10 formed in the base region 5 and the compensation base region 16B formed by the self-line are in contact with each other. It became. This is a compensation base conductor oxide film to ensure connection with the space region 5, 8 is an N-type polycrystalline silicon film, 11 is an aluminum electrode, and 18 is a P-type polycrystalline silicon film.

[Problem to be solved by the invention]

The base resistance between the compensated base region and the emitter region of the conventional bipolar transistor mentioned above is determined by the impurity concentration in the base region 5 in the structure shown in FIG. Although it is necessary to increase the impurity carbon content in the pace region 5, a high concentration base causes problems in terms of transistor characteristics such as a decrease in current amplification factor.

In addition, in the structure shown in FIG. 5, since the compensation base region 16B and the emitter region 10 are in contact with each other, the base resistance is reduced, but the emitter-base junction breakdown voltage is This is determined by the junction breakdown voltage of 16B, which significantly decreases.

Further, when the compensation base region 16B is brought close to the emitter region 10, diffusion is performed in the lateral direction, but at the same time impurity atoms are diffused in the direction of the emitter region. The disadvantage is that it is close to the collector region 2, resulting in a decrease in collector-base junction breakdown voltage and an increase in collector-base capacitance.

A first object of the present invention is to provide a semiconductor device with a reduced base resistance value and a method for manufacturing the same. A second object of the present invention is to provide a semiconductor device and a method for manufacturing the same in which the breakdown voltages of the emitter-base junction and the collector-base junction are less reduced.

[Means to solve the problem]

A first semiconductor device of the present invention includes a collector region of a first conductivity type formed on one main surface of a semiconductor substrate, a base region of a second conductivity type formed in the collector region, and a base region of a second conductivity type formed in the collector region. In a semiconductor device having a first compensation base region of a conductivity type and an emitter region of a first conductivity type formed in the base region, the first compensation base region and the emitter region are provided with the first compensation base region. A second compensation base region connected to the base region and in contact with the emitter region is provided.

A first method for manufacturing a semiconductor device of the present invention includes the steps of forming an epitaxial layer of a first conductivity type to serve as a collector region on one main surface of a semiconductor substrate, and a base region of a second conductivity type in the epitaxial layer. forming a first compensation base region connected to the base region and having a higher cine purity content than the base region; a first compensation base region connected to the first compensation base region in the base region; forming a second compensation base region having a low concentration of fine particles.

A second method for manufacturing a semiconductor device of the present invention includes the steps of sequentially forming an epitaxial layer of a first conductivity type and a first insulating film, which will become a collector region, on one main surface of a semiconductor substrate; a step of sequentially forming a polycrystalline silicon film containing a second conductivity type impurity and a second insulating film on the entire surface after removing a predetermined portion; After forming an opening in a predetermined portion, heat treatment is performed to diffuse impurities in the polycrystalline silicon film to form a first compensation base region in the epitaxial layer, and a second conductivity type impurity is added to the entire surface. A step of forming a glass film containing the aperture and then performing anisotropic etching to leave the glass film only on the side surfaces of the aperture, and a step of performing heat treatment to remove the p impurities from the glass film left on the side surface of the aperture. forming a second compensation base region having a lower cine purity tolerance than the first compensation base region by diffusing into the epitaxial layer and connecting to the first compensation base region.

A second semiconductor device of the present invention includes a collector region of a first conductivity type formed on one main surface of a semiconductor substrate, a base region of a second conductivity type formed in the collector region, and a base region of a second conductivity type formed in the collector region. In a semiconductor device having a first compensation base region of a mold type and an emitter region of a first conductivity type formed in the base region, the first compensation base region is provided between the first compensation base region and the emitter region. A second compensation base region is provided adjacent to the emitter region and adjacent to the emitter region.

A third method for manufacturing a semiconductor device of the present invention includes the steps of sequentially forming an epitaxial layer of a first conductivity type and a first insulating film, which will become a collector region, on one main surface of a semiconductor substrate; a step of sequentially forming a polycrystalline silicon film containing a second conductivity type impurity and a second insulating film on the entire surface after removing a predetermined portion; After forming an opening in a predetermined portion, heat treatment is performed to diffuse the impurity vIJk in the polycrystalline silicon film to form the entire first compensation base region in the epitaxial layer, and the step includes a second conductivity type impurity on the entire surface After forming the glass film, anisotropic etching is performed to leave the glass film only on the side surfaces of the opening, and heat treatment is performed to remove impurities from the glass film left on the side of the opening into the epitaxial layer. forming a second compensation base region which is connected to the first compensation base region and has a lower cine concentration than the first compensation base region; and ion implantation of second conductivity type impurities into the entire surface. A step of forming a base region in the epitaxial layer within the opening, and after forming a third insulating film on the entire surface including the base region, anisotropic etching is performed to form the third insulating film within the opening. The method includes a step of leaving only the surface of the glass film formed on the side surface.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIGS. 1(a) to 1(e) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining a first embodiment of the present invention.

First, as shown in FIG. 1(a), a P-type silicon substrate 1
Arsenic atoms are doped by a diffusion method to form a Nm buried collector region 2, then an N-type epitaxial layer 3 is deposited to a thickness of 1 μm by an epitaxial growth method, and a 9200 OA thick layer is deposited by a thermal oxidation method. A silicon oxide film 4 is formed.

Subsequently, boron ions are selectively implanted into the N-type epitaxial layer by an ion implantation method to form the base region 5.

Next, as shown in FIG. 1(b), boron ions are selectively implanted using an ion implantation method so as to have a higher concentration than the base region 5. 6
form.

Next, as shown in FIG. 1(e), the silicon oxide film 4 on the pace region 5 and the first compensation base region 6 was selectively removed by photolithography, and boron atoms were added by CVD. A boron-containing glass film 7 is deposited in a floating manner at 200 OA.

Next, as shown in FIG. 1 (dl), openings for forming an emitter region communicating with the base region 5 are selectively provided in the boron-containing glass film 7 by photolithography, and then heat treatment is performed at 1000°C. A second compensation base region 9 of P type with a higher concentration than the region is formed by diffusion of boron atoms from a boron-containing glass film.

Next, the N-type polycrystalline silicon film 8 doped with arsenic atoms is
Deposited to a thickness of 2000A by VD method and heated at 900℃
After the emitter region 10 is formed by heat treatment, the N-type polycrystalline silicon film 8 is patterned by photolithography, leaving only the emitter region lo.

When forming the second compensation base region 9 by heat treatment at 1000"C, the boron-containing glass film 4 is heated such that the boron concentration diffused is lower than the boron concentration in the first compensation base region 6. It is necessary to control the oxidizing element concentration in advance.

Next, as shown in FIG. 1(e), a boron-containing glass d
An opening communicating with the first compensation base region 6 is formed in 7 by photolithography, and an aluminum electrode 11 having a thickness of 1 μm is selectively formed to complete the semiconductor device.

In the first embodiment, the second compensation base region is formed using the boron-containing glass film 7. Regions can also be formed. That is,
After forming the first compensating base region 6 on the N-type epitaxial layer 3, the oxide film 4 is formed. After removing the oxide film 4 on the base region in the sixth step, the boron-containing glass film 7 is completely formed, heat-treated, and then pasted. Region 5 is formed. Next, after removing the boron-containing glass film 7 on the emitter region, heat treatment is performed again to form a second compensation base region in the base region.

In the first embodiment configured as described above, since the P-type second compensation base region is formed between the P-type first compensation base region 6 and the emitter region 10, The base resistance between the compensation base region 6 and the emitter region 10 is reduced, and the speed of the device can be increased.

Further, since the impurity concentration of the second compensation base region 9 is lower than that of the first compensation base region, the drop in the emitter-base junction breakdown voltage is small even if it comes into contact with the emitter region 10, and the collector The base capacity will not increase either.

Since this second compensation base can be formed using a boron-containing glass film using a self-alignment process, the process is simple.

FIGS. 2(a) to 2(f) are cross-sectional views of a semiconductor chip shown in order of steps for explaining a second embodiment of the present invention.

First, as shown in FIG. 2(a), arsenic is ion-implanted into a P-type silicon substrate 1 to form an N-type buried collector region 2, and then a zero-order thermal oxidation method is applied to form an N-type epitaxial layer 3. After forming an oxide film 4 with a thickness of 2000 Å and a shift field oxide film 4A by selective oxidation, phosphorous is ion-implanted into the epitaxial layer on the buried collector region 2 to form a collector lead-out region 2A.

Next, as shown in FIGS. 2A and 2B, after openings are formed in the oxide film 4 in the active region, a P-type polycrystalline silicon film 18 doped with boron is deposited to a thickness of 300 OA and patterned. Next, a 3000A thick oxide film (
12 (hereinafter referred to as a CVD oxide film) is deposited.

Next, as shown in FIG. 2(c), openings are selectively formed in the CVD # film 12 and the P-type polycrystalline silicon film 18 on the epitaxial layer by an anisotropic etching method.
After performing a heat treatment of 0"0 to diffuse boron atoms from the P-type polycrystalline silicon film 18 into the epitaxial layer 3 and forming the first compensation base region 6A, the boron-containing glass film 7
is deposited to a thickness of 300OA.

Next, as shown in FIG. 2(d), the boron-containing glass film 7 is etched by anisotropic etching so that it remains on the side walls of the openings of the CVD oxide film 12 and the P-type polycrystalline silicon film 18. Next, heat treatment is performed at 1000°C to diffuse boron atoms from the boron-containing glass film 7A on the side wall of the opening into the epitaxial layer 3 to form a second compensation base region 9A, and after death, silicon ions are implanted into the opening. Boron atoms are doped into the epitaxial layer 3 using a SiSelfa line to form a base region 5.

Next, as shown in FIG. 2(e), a polycrystalline silicon film is deposited to a thickness of 12500A by CVD, arsenic atoms are added into this polycrystalline silicon film by ion implantation, and patterned. Then, an Nff1 polycrystalline silicon film 8 is formed. Next, the N-type polycrystalline silicon film 8 is subjected to heat treatment at 900°C.
The arsenic atoms from are diffused into the base region 5 to form the emitter region IO. Next, openings communicating with the buried collector region 2 and the first compensation base region 6A are selectively formed in the CVD oxide film 12 by photolithography.

Next, as shown in FIG. 2(f), aluminum was deposited to a thickness of 1 μm by sputtering and patterned to form an aluminum electrode 1.
form 1.

This second embodiment has the advantage that the second compensation base region can be formed in a self-aligned manner even in a manufacturing method in which the base region and the emitter region are formed in a cell-aligned manner.

FIGS. 3(a) to 3(a) are cross-sectional views of a semiconductor chip shown in order of steps for explaining a third embodiment of the present invention.

First, as shown in FIG. 3(&), a P-type silicon substrate 1
After selectively doping arsenic atoms by a diffusion method to form an N-type buried collector region 2t-, an N-type epitaxial layer 3t- having a thickness of 1 μm is formed by an epitaxial method.

Next, an oxide film 4 having a thickness of 2000 Å is formed by thermal oxidation and a field oxide film 4At for element isolation is formed by selective oxidation. Furthermore, syringe atoms are selectively added by the acid expansion method to form the collector lead-out region 2A.

Next, as shown in FIG. 3, etc., after selectively forming openings in the oxide film 4 on the substrate surface, a P-type polycrystalline silicon film 18 doped with boron as a P-type impurity is formed to a thickness of 300 OA. It is deposited and patterned to cover the opening. Subsequently, a CVD oxide film 12t-3000A is applied to the entire surface by CVD method.
Deposited to O thickness.

Next, as shown in FIG. 3(e), the CVD oxide film 12 and the P-type polycrystalline silicon film 18 are simultaneously selectively etched by an anisotropic etching method, and the N-type epitaxial layer 3 is etched.
A zero-order heat treatment was performed at 900'O to form an opening leading to the pores, and boron atoms were diffused from the P-type polycrystalline silicon film 18 into the N-type epitaxial layer 3, thereby forming the first compensation base region 6A. Afterwards, the boron-containing glass film 7 was heated to 200O
It is deposited in the fourth layer of A.

Next, as shown in FIG. 3(d), the silica-containing glass film 7 is etched by an anisotropic etching method, and a zero-order one is left on the side walls of the CVD oxide film 12 and the P-type polycrystalline silicon film 18.
After performing heat treatment at 000°C to diffuse boron atoms into the boron-containing glass film 7A on the side wall of the opening and into the N-type epitaxial layer 3 to form a second compensation base region 9A, ion implantation is performed from the opening. Finally, boron atoms are added into the N-type epitaxial layer 3 to form the base region 5.

Next, as shown in FIG. 3(e), an insulating film 14 containing no impurity atoms is deposited to a thickness of 200 OA, etched by anisotropic etching, and left on the boron-containing glass film 7A on the side wall. At the same time, a zero-order polycrystalline silicon film is deposited on the CVD oxide film 12 and the oxide film 4 to a thickness of 200 OA to selectively form all the openings leading to the collector extraction region 2A, and arsenic atoms are added by ion implantation. Then, it is added to this polycrystalline silicon film to form an N-type polycrystalline silicon film 8. Subsequently, heat treatment is performed to diffuse arsenic atoms into the base region 5 to form the emitter region 10.

Next, as shown in Figure 3), an N-type polycrystalline silicon film 8
After patterning, an opening communicating with the P-type polycrystalline silicon film 18 is provided in the CVD oxide film 12, and then an aluminum electrode 11 is selectively formed.

In the embodiment of the wooden tablet 3, since the curve of the boron-containing glass film 7A and the N-type polycrystalline silicon film 8 on the side wall of the opening are separated by the insulating film 14 that does not contain impurity atoms, the second compensation base region 9A A base region 5 is interposed between the emitter region 10 and the emitter region 10 . The distance is controlled by the thickness of the insulating film 14, and in this embodiment, it is very close to about 200 OA. Therefore, it is possible to reduce the base resistance value without deteriorating the emitter-base breakdown voltage.

〔Effect of the invention〕

As explained above, in the present invention, between the first compensation base region and the emitter region, the impurity concentration is lower than that of the first compensation base region which has a high concentration of impurities, and the impurity concentration is also higher than that of the pace region. By forming the second compensation base region having a concentration, the base resistance value between the first compensation base region and the emitter region can be reduced, which is effective in increasing the speed of the device.

Since the impurity concentration of the second compensation base region is lower than the impurity concentration of the first compensation base region, even if it comes into contact with the emitter region, the reduction in the emitter-base junction breakdown voltage is small.

Furthermore, since the second compensation base region is formed shallowly,
There is no decrease in collector-base junction breakdown voltage, and no increase in collector-base capacitance.

Furthermore, by providing the second compensation base region close to the emitter region, the base resistance can be reduced without deteriorating the emitter-base junction breakdown voltage.

[Brief explanation of the drawing]

1 to 3 are cross-sectional views of preliminary semiconductor chips for explaining first to third embodiments of the present invention, and FIGS. 4 and 5 are cross-sectional views of an example of a conventional semiconductor device. DESCRIPTION OF SYMBOLS 1... P-type silicon substrate, 2... N-type buried collector region, 3... N-type epitaxial layer, 4... Silicon oxide film, 4A・・・・・・
Field oxide film, 5...Pace area, 6,6
A...First compensation base area, 7...
Boron-containing glass film, 8...N-type polycrystalline silicon film, 9.9A...M2 compensation base region, 1
0. Old... Emitter region, 11... Aluminum electrode, 12... CVD oxide film, 14... Insulating film containing no impurities, 16A, 16B... ...Compensation base region, 18...P-type polycrystalline silicon film. Agent Patent Attorney Susumu Uchihara -〇

Claims (5)

[Claims] (1) A collector region of a first conductivity type formed on one principal surface of a semiconductor substrate, a base region of a second conductivity type formed within the collector region, and a first compensation base region of a second conductivity type. and an emitter region of a first conductivity type formed in the base region, wherein the first compensation base region is connected to the first compensation base region and is in contact with the emitter region between the first compensation base region and the emitter region. A semiconductor device characterized in that a second compensation base region is provided. (2) A first layer serving as a collector region on one principal surface of the semiconductor substrate.
forming an epitaxial layer of a conductive amount; forming in the epitaxial layer a base region of a second conductivity type and a first compensating base region connected to the base region and having a higher impurity concentration than the base region; A method of manufacturing a semiconductor device, comprising the step of forming a second compensation base region in a base region, which is connected to the first compensation base region and has a lower impurity concentration than the first compensation base region. (3) A first layer serving as a collector region on one principal surface of the semiconductor substrate.
A step of sequentially forming an epitaxial layer of a conductivity type and a first insulating film, and after removing a predetermined portion of the insulating film, a polycrystalline silicon film containing impurities of a second conductivity type and a second insulating film are formed on the entire surface. After forming openings in predetermined portions of the polycrystalline silicon film and the second insulating film that are in contact with the epitaxial layer, heat treatment is performed to diffuse impurities in the polycrystalline silicon film to form the epitaxial layer. a step of forming a first compensation base region within the opening, and a step of forming a glass film containing a second conductivity type impurity on the entire surface and then performing anisotropic etching to leave the glass film only on the side surface of the opening. Then, heat treatment is performed to diffuse impurities into the epitaxial layer from the glass film left on the side surface of the opening, and a second layer is formed which is connected to the first compensation base region and whose impurity concentration is lower than that of the first compensation base region. forming a compensation base region. (4) A collector region of a first conductivity type formed on one principal surface of a semiconductor substrate, a base region of a second conductivity type formed within the collector region, and a first compensation base region of a second conductivity type. and an emitter region of a first conductivity type formed in the base region, wherein the first compensation base region is connected to the first compensation base region and is close to the emitter region between the first compensation base region and the emitter region. A semiconductor device characterized in that a second compensation base region is provided. (5) A first layer serving as a collector region on one main surface of the semiconductor substrate.
A step of sequentially forming an epitaxial layer of a conductivity type and a first insulating film, and after removing a predetermined portion of the insulating film, a polycrystalline silicon film containing impurities of a second conductivity type and a second insulating film are formed on the entire surface. After forming openings in predetermined portions of the polycrystalline silicon film and the second insulating film that are in contact with the epitaxial layer, heat treatment is performed to diffuse impurities in the polycrystalline silicon film into the epitaxial layer. a step of forming a first compensation base region on the entire surface, and a step of forming a glass film containing a second conductivity type impurity over the entire surface and then performing anisotropic etching to leave the glass film only on the side surface of the opening. , heat treatment is performed to diffuse impurities into the epitaxial layer from the glass film left on the side surface of the opening, and a second compensation base region connected to the first compensation base region and having a lower impurity concentration than the first compensation base region is formed. a step of forming a compensation base region; a step of ion-implanting second conductivity type impurities into the entire surface to form a base region in the epitaxial layer within the opening;
forming a third insulating film on the entire surface including the base region, and then performing anisotropic etching to leave the third insulating film only on the surface of the glass film formed on the side surface inside the opening. A method for manufacturing a semiconductor device, characterized in that: