JPH0695573B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JPH0695573B2 JPH0695573B2 JP25087488A JP25087488A JPH0695573B2 JP H0695573 B2 JPH0695573 B2 JP H0695573B2 JP 25087488 A JP25087488 A JP 25087488A JP 25087488 A JP25087488 A JP 25087488A JP H0695573 B2 JPH0695573 B2 JP H0695573B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- semiconductor substrate
- film
- gate electrode
- thin film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 137
- 238000000034 method Methods 0.000 title claims description 22
- 238000004519 manufacturing process Methods 0.000 title description 15
- 239000010408 film Substances 0.000 claims description 88
- 239000000758 substrate Substances 0.000 claims description 47
- 239000010409 thin film Substances 0.000 claims description 27
- 230000003647 oxidation Effects 0.000 claims description 22
- 238000007254 oxidation reaction Methods 0.000 claims description 22
- 238000005530 etching Methods 0.000 claims description 14
- 230000001590 oxidative effect Effects 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 4
- 239000007772 electrode material Substances 0.000 claims description 3
- 230000008569 process Effects 0.000 claims description 3
- 239000013078 crystal Substances 0.000 description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 9
- 229910052581 Si3N4 Inorganic materials 0.000 description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 7
- 230000007547 defect Effects 0.000 description 6
- 239000012535 impurity Substances 0.000 description 6
- 238000001312 dry etching Methods 0.000 description 5
- 239000000126 substance Substances 0.000 description 5
- 230000005684 electric field Effects 0.000 description 4
- 239000012212 insulator Substances 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- -1 for example Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000005549 size reduction Methods 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関し、特に高速動作を
可能とする小型の半導体装置いわゆる絶縁ゲート型電界
効果トランジスタ（以下MOSFETと略称する）を製造する
技術に関するものである。The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a small semiconductor device that enables high-speed operation, a so-called insulated gate field effect transistor (hereinafter abbreviated as MOSFET). It relates to manufacturing technology.
従来の半導体装置の一例を第３図を参照して説明する。
第３図はこの半導体装置の構造断面図であり、１は第１
導電形例えばｐ形の単結晶半導体基板、２はこの半導体
基板１中の埋め込み絶縁膜、３は半導体装置を横方向に
電気的に絶縁するための絶縁膜、４は第１導電形例えば
ｐ形の半導体能動層、５はゲート絶縁膜、６は半導体薄
膜例えば多結晶シリコンを使用したゲート電極、７は第
２導電形例えばｎ形のソース領域、８は第２導電形例え
ばｎ形のドレイン領域、15aと15bはゲート電極６とソー
ス領域７またはドレイン領域８とを電気的に絶縁するた
めの絶縁膜である。また、11はソース電極、12はドレイ
ン電極、13はゲート電極６とソース電極11及びドレイン
電極12の間を相互に電気的に絶縁するための絶縁膜であ
る。An example of a conventional semiconductor device will be described with reference to FIG.
FIG. 3 is a sectional view of the structure of this semiconductor device, where 1 is the first
A single crystal semiconductor substrate having a conductivity type, for example, p type, 2 is an embedded insulating film in the semiconductor substrate 1, 3 is an insulating film for electrically insulating a semiconductor device laterally, and 4 is a first conductivity type, for example, p type. Semiconductor active layer, 5 is a gate insulating film, 6 is a gate electrode using a semiconductor thin film such as polycrystalline silicon, 7 is a second conductivity type, for example, n-type source region, 8 is a second conductivity type, for example, n-type drain region , 15a and 15b are insulating films for electrically insulating the gate electrode 6 from the source region 7 or the drain region 8. Further, 11 is a source electrode, 12 is a drain electrode, and 13 is an insulating film for electrically insulating the gate electrode 6 from the source electrode 11 and the drain electrode 12.
このようなMOSFET構造の半導体装置においては、半導体
装置の能動領域４内の不純物濃度を低くしてゲート絶縁
膜５と半導体能動層４との界面から拡がる空乏層の厚さ
がその能動層４の厚さt1よりも大きくなるように設計す
る。こうすることによつて、半導体能動層４内の電界の
一部が埋め込み絶縁膜２を介して半導体基板１に抜け、
これによつて半導体能動層４内の電界強度が下がる。そ
の結果、半導体能動層４とゲート絶縁膜５の界面におけ
る電子の散乱を少なくすることができて電子の移動度を
大幅に増大できることが知られている。電子の移動度の
改善は半導体装置の性能向上にそのままつながることか
ら、この種の半導体装置の実用化が望まれている。この
半導体装置においてソース及びドレイン領域7,8の厚さt
2を半導体能動層４の厚さt1よりも厚くしてあるのは、
ソース及びドレイン領域7,8の寄生抵抗増大を抑えて半
導体装置の動作能力を最大限に引き出すためである。In such a semiconductor device having a MOSFET structure, the impurity concentration in the active region 4 of the semiconductor device is reduced so that the thickness of the depletion layer extending from the interface between the gate insulating film 5 and the semiconductor active layer 4 is smaller than that of the active layer 4. Design to be larger than the thickness t 1 . By doing so, a part of the electric field in the semiconductor active layer 4 escapes to the semiconductor substrate 1 via the embedded insulating film 2,
As a result, the electric field strength in the semiconductor active layer 4 is lowered. As a result, it is known that the scattering of electrons at the interface between the semiconductor active layer 4 and the gate insulating film 5 can be reduced and the mobility of electrons can be significantly increased. Since the improvement of electron mobility directly leads to the improvement of the performance of the semiconductor device, it is desired to put this type of semiconductor device into practical use. In this semiconductor device, the thickness t of the source and drain regions 7 and 8 is
2 is made thicker than the thickness t 1 of the semiconductor active layer 4,
This is to suppress the increase in parasitic resistance of the source and drain regions 7 and 8 and maximize the operating capability of the semiconductor device.
ここで、かかる構造を実現するための従来の製造方法の
一例を第４図に示す。この方法は、まず第４図（ａ）に
示すように、半導体基板１の主面側に半導体層を残すべ
く半導体基板の内部に例えば酸素をイオン注入すること
によつて、半導体基板１の主面側に埋め込み絶縁膜２と
半導体層1aを形成する。その後、半導体基板１の主面側
に個別の半導体装置間を電気的に絶縁分離するための絶
縁膜３を設け、半導体装置を製作する領域に絶縁膜31を
形成し、この後半導体基板１の主面側をレジスト32で覆
い、将来ゲート絶縁膜を形成する領域のレジストのみを
除去して絶縁膜31を露出させる。その後絶縁膜31のうち
露出した部分をエツチングで除去して半導体層1aを露出
させ、更に半導体層1aを反応性イオンエツチングあるい
は他のイオンビームエツチング等のエツチング法により
所定の深さまで掘り、埋め込み絶縁膜２上に所定の厚さ
の半導体層1bを残す。このようにして断面が矩形の溝33
を形成する。また半導体1bを所定の不純物濃度の第１導
電形例えばｐ形にすべく領域1b中に例えばイオン注入法
により不純物を導入し、熱処理により不純物を活性化す
る。Here, an example of a conventional manufacturing method for realizing such a structure is shown in FIG. In this method, as shown in FIG. 4 (a), first, for example, oxygen is ion-implanted into the inside of the semiconductor substrate to leave a semiconductor layer on the main surface side of the semiconductor substrate 1. The buried insulating film 2 and the semiconductor layer 1a are formed on the surface side. After that, the insulating film 3 for electrically insulating and separating the individual semiconductor devices from each other is provided on the main surface side of the semiconductor substrate 1, and the insulating film 31 is formed in the region where the semiconductor device is manufactured. The main surface side is covered with a resist 32, and only the resist in a region where a gate insulating film will be formed in the future is removed to expose the insulating film 31. After that, the exposed portion of the insulating film 31 is removed by etching to expose the semiconductor layer 1a, and the semiconductor layer 1a is further dug to a predetermined depth by an etching method such as reactive ion etching or other ion beam etching to perform embedded insulation. The semiconductor layer 1b having a predetermined thickness is left on the film 2. In this way, a groove with a rectangular cross section 33
To form. Further, impurities are introduced into the region 1b by, for example, an ion implantation method so that the semiconductor 1b has a first conductivity type having a predetermined impurity concentration, for example, p-type, and the impurities are activated by heat treatment.
次に第４図（ｂ）に示すように、溝33の底を含む側壁33
aを酸化処理してゲート絶縁膜５を形成すると共に厚さt
1の半導体能動層４を形成する。その後半導体基板１の
主面側にゲート電極用半導体膜例えば多結晶シリコン膜
を形成し、所定の寸法を有するレジスト等のマスクを形
成した後に前記多結晶シリコン膜を加工してゲート電極
６を形成する。次にソース及びドレイン領域となる半導
体領域に不純物を添加しかつ活性化して第２導電形例え
ばｎ形のソース領域７及びドレイン領域８を形成する。
この後は通常の製造工程に従つて、配線用電極を形成す
れば第３図に示すようなMOSFET構造の半導体装置を形成
することができる。Next, as shown in FIG. 4 (b), the side wall 33 including the bottom of the groove 33 is formed.
A is oxidized to form the gate insulating film 5 and the thickness t
The semiconductor active layer 4 of 1 is formed. After that, a semiconductor film for a gate electrode, for example, a polycrystalline silicon film is formed on the main surface side of the semiconductor substrate 1, a mask such as a resist having a predetermined size is formed, and then the polycrystalline silicon film is processed to form a gate electrode 6. To do. Then, impurities are added to the semiconductor regions to be the source and drain regions and activated to form the source region 7 and the drain region 8 of the second conductivity type, for example, the n type.
After that, if a wiring electrode is formed according to a normal manufacturing process, a semiconductor device having a MOSFET structure as shown in FIG. 3 can be formed.
しかし、上述した従来の技術においては次のような問題
点があつた。すなわち、第１に、上記の工程において述
べたように、ゲート絶縁膜５を形成する領域はイオン・
ビーム等のドライ・エツチング法により掘られてきた。
ドライ・エツチング法は一般的にエツチングされて露出
した半導体面1b近傍に高い密度の結晶欠陥を誘発するこ
とが知られている。これらの結晶欠陥はソース・ドレイ
ン間の漏れ電流を著しく増大させる。また、ゲート絶縁
膜５と半導体基板１との界面状態が結晶欠陥のために悪
化し、これによつて電子または正孔の移動度が劣化す
る。しかし、第３図の構造を実現するにはドライ・エツ
チング法以外になく、従つて、このような構造と製造方
法では、動作特性の優れた半導体装置を実現することは
困難である。However, the above-mentioned conventional technique has the following problems. That is, first, as described in the above step, the region where the gate insulating film 5 is formed is formed of ions.
It has been dug by the dry etching method such as beam.
It is known that the dry etching method generally induces a high density of crystal defects in the vicinity of the semiconductor surface 1b exposed by etching. These crystal defects significantly increase the leakage current between the source and drain. In addition, the interface state between the gate insulating film 5 and the semiconductor substrate 1 is deteriorated due to crystal defects, which deteriorates the mobility of electrons or holes. However, the dry etching method is the only method for realizing the structure shown in FIG. 3. Therefore, it is difficult to realize a semiconductor device having excellent operating characteristics with such a structure and manufacturing method.
第２に、第４図（ｂ）に示したように、ゲート電極６と
ソース領域７及びドレイン領域８とを隔てている絶縁膜
15aと15bは、事実上ゲート絶縁膜５を酸化法で形成する
のと同時に形成される。半導体装置の高性能化の観点か
らはゲート電極寸法の小型化と共にゲート絶縁膜の薄層
化が必須であつて、該絶縁膜15aと15bを厚くすることは
困難であり、半導体装置のゲート寸法の小型化に伴つて
ゲート電極６とソース領域７の間及びゲート電極６とド
レイン領域８の間の重なり容量の占める割合が大きくな
るため、半導体装置の高速動作の妨げになるという欠点
があつた。Second, as shown in FIG. 4B, an insulating film that separates the gate electrode 6 from the source region 7 and the drain region 8.
Virtually 15a and 15b are formed at the same time when the gate insulating film 5 is formed by the oxidation method. From the viewpoint of improving the performance of semiconductor devices, it is essential to reduce the size of the gate electrode and thin the gate insulating film, and it is difficult to thicken the insulating films 15a and 15b. As the size of the semiconductor device becomes smaller, the proportion of the overlapping capacitance between the gate electrode 6 and the source region 7 and between the gate electrode 6 and the drain region 8 increases, which is a drawback that the high-speed operation of the semiconductor device is hindered. .
本発明は以上のような点に歓みてなされたもので、その
目的は、ゲート絶縁膜を形成する半導体領域に発生する
結晶欠陥を最小限に抑えて、小型でかつ動作の高速な半
導体装置を安定に製造する方法を提供することにある。The present invention has been made in light of the above points, and an object thereof is to provide a small-sized and high-speed operation semiconductor device by minimizing crystal defects generated in a semiconductor region forming a gate insulating film. It is to provide a stable manufacturing method.
上記の目的を達成するため、本発明に係る半導体装置の
製造方法は、半導体中に絶縁物層が埋め込まれて該絶縁
物上に半導体層を有する半導体基板の主面に耐酸化性薄
膜を堆積する工程と、該半導体基板上の前記耐酸化性薄
膜のうちゲート電極を配置する平面領域をエツチングし
て除去する工程と、前記耐酸化性薄膜の一部を除去した
該半導体基板を酸化性雰囲気に晒してゲート電極を配置
するために前記耐酸化性薄膜を除去した領域に所定の厚
さの選択酸化膜を形成する工程と、前記の工程により形
成されたゲート電極を配置すべき領域の前記選択酸化膜
のみを除去して該半導体基板のうち前記選択酸化膜下の
半導体層を露出する工程と、該半導体基板を酸化性雰囲
気に晒して前記半導体層の露出部分を酸化してゲート絶
縁膜を形成する工程と、該半導体基板の少なくとも主面
側にゲート電極材料として使用する半導体薄膜を堆積す
る工程と、該半導体基板の主面側において前記耐酸化性
薄膜が露出するまで前記半導体薄膜をエツチングする工
程と、該半導体基板を酸化性雰囲気に晒すことにより、
露出した前記半導体薄膜の表面近傍のみを酸化する工程
と、該半導体基板上の前記耐酸化性薄膜を除去する工程
と、該半導体基板の少なくとも主面側に残存する前記ゲ
ート電極用半導体薄膜のうち露出領域のみを選択的にエ
ツチングして除去する工程とを含むものである。In order to achieve the above-mentioned object, a method for manufacturing a semiconductor device according to the present invention is a method of depositing an oxidation resistant thin film on a main surface of a semiconductor substrate in which an insulator layer is embedded in a semiconductor and the semiconductor layer is provided on the insulator. And a step of removing a planar region of the oxidation-resistant thin film on the semiconductor substrate where the gate electrode is arranged, and a step of removing the oxidation-resistant thin film from the semiconductor substrate in an oxidizing atmosphere. Exposed to the surface of the gate electrode to form a selective oxide film having a predetermined thickness in the area where the oxidation resistant thin film is removed, and the gate electrode formed by the above step is to be arranged in the area. A step of removing only the selective oxide film to expose a semiconductor layer of the semiconductor substrate below the selective oxide film; and exposing the semiconductor substrate to an oxidizing atmosphere to oxidize an exposed portion of the semiconductor layer to form a gate insulating film Forming A step of depositing a semiconductor thin film used as a gate electrode material on at least the main surface side of the semiconductor substrate, and a step of etching the semiconductor thin film until the oxidation resistant thin film is exposed on the main surface side of the semiconductor substrate. By exposing the semiconductor substrate to an oxidizing atmosphere,
A step of oxidizing only the exposed surface of the semiconductor thin film, a step of removing the oxidation resistant thin film on the semiconductor substrate, and a step of removing the gate electrode semiconductor thin film remaining on at least the main surface side of the semiconductor substrate. And a step of selectively etching and removing only the exposed region.
したがつて、本発明においては、ソース電極界面及びド
レイン電極電界の位置をゲート絶縁膜と半導体能動層の
界面の位置よりも高くするためにゲート絶縁膜を形成す
る領域に溝を形成するに当り、半導体基板の酸化と薬液
による酸化物の除去を用いることにより、ゲート絶縁膜
直下の半導体界面に半導体装置の動作特性を劣化させる
結晶欠陥を発生させることはない。また、ゲート絶縁物
上にゲート電極を設けるに当たつて、ゲート電極形成用
のマスクを用いないゲート電極を自己整合てきに形成で
きるとともに、ゲート電極とソース領域及びドレイン領
域の間に厚い絶縁膜を設ける間隙をゲート電極を加工す
る際に同時に形成できる。Therefore, in the present invention, in order to make the position of the electric field of the source electrode and the electric field of the drain electrode higher than the position of the interface of the gate insulating film and the semiconductor active layer, a groove is formed in the region where the gate insulating film is formed. By using the oxidation of the semiconductor substrate and the removal of the oxide by the chemical solution, crystal defects that deteriorate the operating characteristics of the semiconductor device are not generated at the semiconductor interface immediately below the gate insulating film. Further, in providing the gate electrode on the gate insulator, a gate electrode without using a mask for forming the gate electrode can be formed in a self-aligned manner, and a thick insulating film is formed between the gate electrode and the source region and the drain region. It is possible to form the gap for forming the gap at the same time when the gate electrode is processed.
以下、本発明の実施例を第１図と第２図を用いて詳細に
説明する。Hereinafter, an embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.
第１図は本発明の方法により実現できる半導体装置の一
例を示す構造断面図である。同図において、１は第１導
電形例えばｐ形の単結晶半導体基板、２はこの半導体基
板１中の埋め込み絶縁膜、３は半導体装置を横方向に電
気的に絶縁するための絶縁膜、４は第１導電形例えばｐ
形の半導体能動層、５はゲート絶縁膜、６は半導体薄膜
を使用したゲート電極である。また、７は第２導電形例
えばｎ形のソース領域、８は同じくｎ形のドレイン領
域、９はゲート電極６上の絶縁膜、10aと10bはゲート電
極６の側壁に設けた絶縁膜、11はソース電極、12はドレ
イン電極、13はゲート電極６とソース電極11及びドレイ
ン電極12の間を相互に電気的に絶縁するための絶縁膜で
ある。FIG. 1 is a structural sectional view showing an example of a semiconductor device which can be realized by the method of the present invention. In the figure, reference numeral 1 is a first-conductivity-type, for example, p-type single crystal semiconductor substrate, 2 is a buried insulating film in the semiconductor substrate 1, 3 is an insulating film for electrically insulating a semiconductor device laterally, and 4 Is the first conductivity type, for example p
-Shaped semiconductor active layer, 5 is a gate insulating film, and 6 is a gate electrode using a semiconductor thin film. Further, 7 is a second conductivity type, for example, n-type source region, 8 is also an n-type drain region, 9 is an insulating film on the gate electrode 6, 10a and 10b are insulating films provided on the sidewalls of the gate electrode 6, 11 Is a source electrode, 12 is a drain electrode, and 13 is an insulating film for electrically insulating the gate electrode 6 from the source electrode 11 and the drain electrode 12.
次に、かかるMOSFET構造を実現するための本発明の製造
方法の一例を第２図に示す。ここで、まず第２図（ａ）
に示すように、例えば単結晶シリコンのような半導体基
板１において半導体基板の主面側に半導体層を残すべ
く、半導体基板の内部に例えば酸素をイオン注入して半
導体基板の主面側に埋め込み酸化膜２と半導体層1aとを
形成する。次に半導体基板１の主面側に個別の半導体装
置間を電気的に絶縁分離するための絶縁膜３を例えば選
択強化法により設け、半導体装置を製作する領域に半導
体酸化膜21を形成し、この後半導体基板１の主面側に耐
酸化性を有する膜例えばシリコン窒化膜22を形成し、更
にその上をレジスト23で覆う。次に、将来ゲート電極を
形成する所定の幅（図中:L1）の領域のレジストのみを
除去してシリコン窒化膜22を露出させる。その後シリコ
ン窒化膜22のうち露出した部分を例えば薬液によるエツ
チングで除去して酸化膜21を露出させる。Next, FIG. 2 shows an example of a manufacturing method of the present invention for realizing such a MOSFET structure. Here, first, FIG. 2 (a)
As shown in FIG. 3, in order to leave a semiconductor layer on the main surface side of the semiconductor substrate in the semiconductor substrate 1 such as single crystal silicon, for example, oxygen is ion-implanted into the semiconductor substrate and buried oxidation is performed on the main surface side of the semiconductor substrate. The film 2 and the semiconductor layer 1a are formed. Next, an insulating film 3 for electrically insulating and separating the individual semiconductor devices is provided on the main surface side of the semiconductor substrate 1 by, for example, a selective strengthening method, and a semiconductor oxide film 21 is formed in a region where the semiconductor device is manufactured. After that, a film having oxidation resistance, for example, a silicon nitride film 22 is formed on the main surface side of the semiconductor substrate 1, and a resist 23 is further covered thereover. Then, the silicon nitride film 22 is exposed by removing only the resist in a region having a predetermined width (L 1 in the drawing) where a gate electrode will be formed in the future. Thereafter, the exposed portion of the silicon nitride film 22 is removed by etching with a chemical solution, for example, to expose the oxide film 21.
次いで第２図（ｂ）に示すように、半導体基板１上のレ
ジスト23を除去した後、この半導体基板１を酸化性雰囲
気に晒してシリコン窒化膜22が除去された部分のみを選
択的に所定の時間酸化する。このようにして選択酸化膜
24を形成することによつて、半導体層1aのうちゲート電
極を形成する領域の半導体厚さが所定の厚さとなるよう
に製造条件を調整する。この時選択酸化法の特徴とし
て、シリコン窒化膜22の下部に距離L2だけ酸化膜が横方
向に成長する。Then, as shown in FIG. 2B, after removing the resist 23 on the semiconductor substrate 1, the semiconductor substrate 1 is exposed to an oxidizing atmosphere to selectively prescribe only the portion where the silicon nitride film 22 is removed. Oxidize for a time. In this way the selective oxide film
By forming 24, the manufacturing conditions are adjusted so that the semiconductor thickness of the region of the semiconductor layer 1a where the gate electrode is formed becomes a predetermined thickness. At this time, a feature of the selective oxidation method is that an oxide film laterally grows below the silicon nitride film 22 by a distance L 2 .
次に第２図（ｃ）に示すように、選択酸化膜24を例えば
フツ化水素酸を含む薬液によるエツチングにより除去
し、露出した半導体層1aの表面を酸化してゲート絶縁膜
５を形成し、その後半導体基板１の主面側にゲート電極
用の半導体膜例えば多結晶シリコン膜25を選択酸化膜24
が存在していた領域が埋まるように例えば減圧CVD法に
より堆積する。この段階で、所定の厚さをもつた半導体
能動層４がゲート酸化膜５の直下に形成される。Next, as shown in FIG. 2 (c), the selective oxide film 24 is removed by etching with a chemical solution containing hydrofluoric acid, and the exposed surface of the semiconductor layer 1a is oxidized to form a gate insulating film 5. Then, a semiconductor film for a gate electrode, for example, a polycrystalline silicon film 25 is formed on the main surface side of the semiconductor substrate 1 by a selective oxide film 24.
Is deposited by, for example, a low pressure CVD method so as to fill the region in which the existent. At this stage, the semiconductor active layer 4 having a predetermined thickness is formed immediately below the gate oxide film 5.
次いで第２図（ｄ）に示すように、半導体基板１の主面
側の多結晶シリコン膜25を例えば反応性イオンエツチン
グ法のような異方性ドライエツチング法により、選択酸
化膜24が存在した領域にのみに残るようにエツチングす
る。その後、半導体基板１を酸化性雰囲気に晒して、前
記工程で残された多結晶シリコン膜251のうち露出して
いる部分のみに絶縁膜つまり酸化膜９を形成する。Then, as shown in FIG. 2D, the selective oxide film 24 was formed on the polycrystalline silicon film 25 on the main surface side of the semiconductor substrate 1 by anisotropic dry etching such as reactive ion etching. Etching so that it remains only in the area. Then, exposing the semiconductor substrate 1 to an oxidizing atmosphere, only an insulating film clogging oxide film 9 exposed portions of the the polycrystalline silicon film left in step 25 1.
次に第２図（ｅ）に示すように、シリコン窒化膜22を例
えば加熱したリン酸を含む薬液によるエツチングにより
除去した後、例えば異方性ドライエツチング法により、
酸化膜９をマスクとして下部のゲート絶縁膜５が露出す
るまで多結晶シリコン251をエツチングしてゲート電極
６を形成する。Next, as shown in FIG. 2 (e), the silicon nitride film 22 is removed by etching with a chemical solution containing heated phosphoric acid, and then, for example, by anisotropic dry etching.
The lower part of the gate insulating film 5 and the oxide film 9 as a mask to form a gate electrode 6 by etching the polycrystalline silicon 25 1 to expose.
次に第４図（ｆ）に示すように、ゲート電極６の露出し
た部分を酸化して絶縁膜10a及10bで覆い、この後、ソー
ス及びドレイン領域となる半導体領域に不純物をイオン
注入法により添加しかつ活性化してｎ形のソース及びド
レイン領域7,8を形成し、更に半導体基板の主面側に絶
縁膜例えばリンドープ酸化膜13を形成する。その後は通
常の半導体装置の製造方法に従つてソース電極11及びド
レイン電極12を形成することにより、第１図に示すよう
なMOSFET構造の半導体装置を作ることができる。Next, as shown in FIG. 4 (f), the exposed portion of the gate electrode 6 is oxidized and covered with the insulating films 10a and 10b, and then impurities are ion-implanted into the semiconductor regions to be the source and drain regions. Addition and activation are performed to form n-type source and drain regions 7 and 8, and an insulating film such as a phosphorus-doped oxide film 13 is further formed on the main surface side of the semiconductor substrate. After that, the source electrode 11 and the drain electrode 12 are formed according to a usual method for manufacturing a semiconductor device, whereby a semiconductor device having a MOSFET structure as shown in FIG. 1 can be manufactured.
上記実施例の製造方法によると、一番はじめに半導体基
板上に形成された耐酸化性薄膜の溝寸法L1が最終的に形
成されるゲート電極幅とほぼ等しくなる。従つて、該溝
寸法L1を小さくすればするほど半導体装置の高性能化が
可能となる。このL1は現状のリソグラフイ技術の限界ま
で設定可能であり、今後のリソグラフイ技術の発展を考
慮すれば、本発明の製造方法による半導体装置のゲート
電極寸法の小型化に限界はない。According to the manufacturing method of the above-described embodiment, the groove dimension L 1 of the oxidation resistant thin film formed on the semiconductor substrate first becomes substantially equal to the width of the finally formed gate electrode. Therefore, the smaller the groove dimension L 1 , the higher the performance of the semiconductor device. This L 1 can be set up to the limit of the current lithographic technique, and in consideration of future development of the lithographic technique, there is no limit to downsizing the gate electrode size of the semiconductor device by the manufacturing method of the present invention.
なお、本発明は上述の実施例にのみ限定されるものでは
なく、例えば半導体中に絶縁物層を埋め込み該絶縁物上
に半導体層を有する半導体基板上の主面に他の薄膜を介
在させず耐酸化性薄膜を形成したり、あるいはゲート電
極材料に多結晶シリコン以外の非晶質シリコン等の半導
体薄膜を用いたりすることなど、特許請求の範囲に記載
された範囲内において種々変更し得るものである。It should be noted that the present invention is not limited to the above-described embodiments, and for example, an insulating layer is embedded in a semiconductor and another thin film is not provided on the main surface of a semiconductor substrate having a semiconductor layer on the insulating layer. Various changes can be made within the scope of the claims such as forming an oxidation resistant thin film or using a semiconductor thin film such as amorphous silicon other than polycrystalline silicon for the gate electrode material. Is.
以上説明したように本発明によれば、ソース電極界面及
びドレイン電極界面の位置をゲート絶縁膜と半導体能動
層の界面の位置よりも高くする構造を有する半導体装置
の製造方法においてそのゲート絶縁膜を形成する領域に
溝を形成するに当り、半導体基板の酸化と薬液による酸
化物の除去を利用することにより、次のような効果が得
られる。As described above, according to the present invention, in the method of manufacturing a semiconductor device having a structure in which the position of the interface between the source electrode and the drain electrode is higher than the position of the interface between the gate insulating film and the semiconductor active layer, the gate insulating film is formed. The following effects can be obtained by utilizing the oxidation of the semiconductor substrate and the removal of the oxide by the chemical solution in forming the groove in the region to be formed.
（１） ゲート絶縁膜を形成する領域に結晶欠陥が誘発
されない。そのため、ソース・ドレイン間の漏れ電流が
増大しない。また、ゲート絶縁膜と半導体基板との界面
状態が良好であるため、電子または正孔の移動度が劣化
することもない。(1) Crystal defects are not induced in the region where the gate insulating film is formed. Therefore, the leakage current between the source and drain does not increase. Further, since the state of the interface between the gate insulating film and the semiconductor substrate is good, the mobility of electrons or holes does not deteriorate.
（２） 耐酸化性薄膜の溝を形成するためのマスクだけ
でゲート電極の位置と寸法を一義的に決定できるため、
半導体装置のゲート電極寸法の小型化に基本的に限界は
なく、半導体装置の高性能化にきわめて有利である。(2) Since the position and size of the gate electrode can be uniquely determined only by the mask for forming the groove of the oxidation resistant thin film,
There is basically no limit to the size reduction of the gate electrode of the semiconductor device, which is extremely advantageous for improving the performance of the semiconductor device.
（３） ゲート電極とソース領域及びドレイン領域とを
隔てている絶縁膜を厚くすることが容易であり、ゲート
・ソース間及びゲート・ドレイン間の重なり容量を低減
できるので、半導体装置の高速動作に有利である。(3) Since it is easy to increase the thickness of the insulating film that separates the gate electrode from the source region and the drain region, and the overlapping capacitance between the gate and the source and between the gate and the drain can be reduced, the semiconductor device can operate at high speed. It is advantageous.
第１図および第２図は本発明の製造方法の一実施例を説
明するための半導体装置の構造断面図およびその工程断
面図、第３図および第４図は従来の一例を示す半導体装
置の構造断面図およびその一部工程断面図である。 １……単結晶半導体基板、２……埋め込み絶縁膜、３…
…絶縁膜、４……半導体能動層、５……ゲート絶縁膜、
６……ゲート電極、７……ソース領域、８……ドレイン
領域、9,10a,10b……絶縁膜、11……ソース電極、12…
…ドレイン電極、13……絶縁膜、21……半導体酸化膜、
22……シリコン窒化膜（耐酸化性薄膜）、23……レジス
ト、24……選択酸化膜、25……多結晶シリコン膜。1 and 2 are structural cross-sectional views of a semiconductor device and process cross-sectional views thereof for explaining one embodiment of the manufacturing method of the present invention, and FIGS. 3 and 4 show a conventional semiconductor device. It is a structure sectional view and its partial process sectional view. 1 ... Single crystal semiconductor substrate, 2 ... Embedded insulating film, 3 ...
... Insulating film, 4 ... Semiconductor active layer, 5 ... Gate insulating film,
6 ... Gate electrode, 7 ... Source region, 8 ... Drain region, 9,10a, 10b ... Insulating film, 11 ... Source electrode, 12 ...
… Drain electrode, 13 …… Insulating film, 21 …… Semiconductor oxide film,
22 …… Silicon nitride film (oxidation-resistant thin film), 23 …… Resist, 24 …… Selective oxide film, 25 …… Polycrystalline silicon film.
Claims (1)
物上に半導体層を有する半導体基板の主面に耐酸化性薄
膜を堆積する工程と、該半導体基板上の前記耐酸化性薄
膜のうちゲート電極を配置する平面領域をエツチングし
て除去する工程と、前記耐酸化性薄膜の一部を除去した
該半導体基板を酸化性雰囲気に晒してゲート電極を配置
するために前記耐酸化性薄膜を除去した領域に所定の厚
さの選択酸化膜を形成する工程と、前記の工程により形
成されたゲート電極を配置すべき領域の前記選択酸化膜
のみを除去して該半導体基板のうち前記選択酸化膜下の
半導体層を露出する工程と、該半導体基板を酸化性雰囲
気に晒して前記半導体層の露出部分を酸化してゲート絶
縁膜を形成する工程と、該半導体基板の少なくとも主面
側にゲート電極材料として使用する半導体薄膜を堆積す
る工程と、該半導体基板の主面側において前記耐酸化性
薄膜が露出するまで前記半導体薄膜をエツチングする工
程と、該半導体基板を酸化性雰囲気に晒すことにより、
露出した前記半導体薄膜の表面近傍のみを酸化する工程
と、該半導体基板上の前記耐酸化性薄膜を除去する工程
と、該半導体基板の少なくとも主面側に残存する前記ゲ
ート電極用半導体薄膜のうち露出領域のみを選択的にエ
ツチングして除去する工程とを含むことを特徴とする半
導体装置の製造方法。1. A step of depositing an oxidation resistant thin film on a main surface of a semiconductor substrate having a semiconductor layer embedded in the semiconductor by embedding an insulating layer in the semiconductor, and the oxidation resistant thin film on the semiconductor substrate. A step of etching and removing a planar region in which the gate electrode is arranged, and the oxidation resistance for exposing the semiconductor substrate from which a part of the oxidation resistant thin film has been removed to an oxidizing atmosphere to arrange the gate electrode. Forming a selective oxide film having a predetermined thickness in the region where the thin film is removed; and removing only the selective oxide film in the region where the gate electrode formed by the above process is to be arranged, Exposing the semiconductor layer under the selective oxide film, exposing the semiconductor substrate to an oxidizing atmosphere to oxidize the exposed portion of the semiconductor layer to form a gate insulating film, and at least the main surface side of the semiconductor substrate Gate electrode material Depositing a semiconductor thin film to be used as a step of etching the semiconductor thin film to said oxidation resistant film on the main surface side of the semiconductor substrate is exposed, by exposing the semiconductor substrate to an oxidizing atmosphere,
A step of oxidizing only the exposed surface of the semiconductor thin film, a step of removing the oxidation resistant thin film on the semiconductor substrate, and a step of removing the gate electrode semiconductor thin film remaining on at least the main surface side of the semiconductor substrate. And a step of selectively etching and removing only the exposed region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25087488A JPH0695573B2 (en) | 1988-10-06 | 1988-10-06 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25087488A JPH0695573B2 (en) | 1988-10-06 | 1988-10-06 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0298940A JPH0298940A (en) | 1990-04-11 |
| JPH0695573B2 true JPH0695573B2 (en) | 1994-11-24 |
Family
ID=17214296
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25087488A Expired - Fee Related JPH0695573B2 (en) | 1988-10-06 | 1988-10-06 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0695573B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5342796A (en) * | 1991-05-28 | 1994-08-30 | Sharp Kabushiki Kaisha | Method for controlling gate size for semiconduction process |
| JP2731056B2 (en) * | 1991-10-09 | 1998-03-25 | シャープ株式会社 | Method for manufacturing thin film transistor |
-
1988
- 1988-10-06 JP JP25087488A patent/JPH0695573B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0298940A (en) | 1990-04-11 |
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