JP2000323489A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to form a high-frequency transistor having small parasitic collector resistance and a highly dielectric transistor on the same substrate even if the substrate has a thick epitaxial layer. SOLUTION: A second reverse-conductivity buried collector layer 22 is formed which is raised up from a first reverse-conductivity buried collector layer 21. A reverse-conductivity pedestal collector layer 102 and a first conductivity base layer 8 are formed at the position contacting the second reverse- conductivity buried collector layer 22. This can prevent a Kirk effect to thereby increase the film thickness of an epitaxial collector layer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a high-frequency and high-speed bipolar transistor and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, high-frequency and high-speed information communication devices have been developed, and semiconductor devices used in these devices have been required to have improved high-frequency characteristics. for that reason,
Techniques have been announced that enable reduction of the parasitic collector resistance and suppression of the Kirk effect and improve high-frequency characteristics. For example, Japanese Patent Application Laid-Open No. Hei 5-267317 and Japanese Patent No.
No. 48898 proposes a structure and a manufacturing method of a bipolar transistor provided with a pedestal collector layer.

Hereinafter, a semiconductor device having a conventional bipolar transistor and a method of manufacturing the same will be described.
FIG. 8 is a sectional view showing the structure of a conventional semiconductor device. This semiconductor device includes a P-type silicon substrate 1, an N-type buried collector layer 2, an N-type silicon epitaxial layer 3, an element isolation oxide film 4, an N-type buried collector lead layer 5, a base lead electrode 6, a P-type external base layer 7. , A P-type intrinsic base layer 8, an insulating film 9, a sidewall insulating film 10, an emitter diffusion layer 11, an emitter electrode 12, and pedestal collector layers 102 to 104.

FIG. 9 is an explanatory view showing an impurity concentration distribution centered on the pedestal collector layer in the depth direction at the position A in FIG. In order to manufacture a semiconductor device having such a structure, first, an N-type buried collector layer 2 is formed on a P-type silicon substrate 1, and then an N-type silicon epitaxial layer 3 is grown. After forming the element isolation oxide film 4, an N-type buried collector lead-out layer 5 is formed. Next, for example, phosphorus ions are implanted at an energy of 500 to 600 KeV, and the pedestal collector layer 104 is selectively formed in a region having a depth of 0.5 to 0.6 μm. Thereafter, a base extraction electrode 6 provided with an opening for forming an emitter, a P-type external base layer 7, and an insulating film 9 are formed. Next, boron ion implantation is performed at 10 to 20 K from the opening for forming the emitter.
The process is performed at about eV to form the P-type intrinsic base layer 8. Similarly, phosphorus ions are implanted at about 300 to 400 KeV to form a pedestal collector layer 103 in a region having a depth of 0.4 to 0.5 μm.

After that, a sidewall insulating film 10 is formed on the base lead electrode 6 and the insulating film 9. Immediately below the reduced emitter formation region, phosphorus ion implantation is performed at 200 to 250 KeV, and 0.25 to 0.
The pedestal collector 102 is formed in a region having a depth of 35 μm. After that, the emitter diffusion layer 11 and the emitter electrode 1
2 is formed.

[0006] In such a semiconductor device, pedestal collector layers 102 to 104 are sequentially arranged under the P-type intrinsic base layer 8 up to the N-type buried collector layer 2, thereby reducing the parasitic collector resistance of the transistor. The pedestal collector layer 102 is formed directly under the P-type intrinsic base layer 8 by using an ion implantation method with good controllability, and contributes to suppression of the Kirk effect.

[0007]

However, in the structure in which the pedestal collector layers are arranged in order in the depth direction, the thickness of the intrinsic base layer 8 and the epitaxial collector layer of the N-type buried collector layer 2 as in the conventional example described above are reduced. 0.4-0.
When the thickness is about 6 μm, the above-described effects can be obtained. But,
In order to form a high-frequency transistor and a high breakdown voltage transistor on the same substrate, for example, when the epitaxial collector layer is thickened to about 2 μm, the pedestal collector layer 1
It is difficult to form the layers 02 to 104 at a depth of about 1.5 to 1.6 μm. For this reason, there has been a problem that the high-frequency transistor and the high breakdown voltage transistor cannot be formed on the same substrate.

SUMMARY OF THE INVENTION The present invention has been made in view of such a conventional problem. Even when a thick epitaxial collector layer is formed, a parasitic collector between an intrinsic base layer and a buried collector layer of a high-frequency transistor is provided. It is an object of the present invention to realize a semiconductor device including a high-frequency transistor in which the resistance is reduced and the Kirk effect is suppressed, and to realize a manufacturing method thereof.

[0009]

According to a first aspect of the present invention, there is provided a reverse conductive type buried collector layer formed on a semiconductor substrate of one conductivity type, and a reverse conductive type buried collector layer formed on the reverse conductive type buried collector layer. A collector layer, a one-conductivity-type base layer formed on the reverse-conductivity-type collector layer, and a reverse-conductivity-type pedestal collector layer formed immediately below the one-conductivity-type base layer, The reverse conductivity type buried collector layer is composed of two or more types of reverse conductivity type impurity diffusion layers, and at least one of the reverse conductivity type impurity diffusion layers is arranged at a position in contact with the reverse conductivity type pedestal collector layer. It is characterized by the following.

According to a second aspect of the present invention, a step of forming a first reverse conductivity type buried collector layer with a first reverse conductivity type impurity in a one conductivity type semiconductor substrate and a step of forming a second reverse conductivity type buried collector layer are provided. Forming a second reverse conductivity type buried collector layer, and forming a reverse conductivity type collector layer on the first reverse conductivity type buried collector layer and the second reverse conductivity type buried collector layer; Forming a reverse conductivity type pedestal collector layer at a position in contact with the first reverse conductivity type buried collector layer or the second reverse conductivity type buried collector layer from a predetermined opening in the surface of the reverse conductivity type collector layer; And forming a one conductivity type base layer on the reverse conductivity type pedestal collector layer from the hole.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to an embodiment of the present invention and a method for manufacturing the same will be described with reference to the drawings. FIG. 1 is a cross-sectional view showing the structure of the semiconductor device according to the present embodiment, and the same parts as those in FIG. FIG. 2 is an explanatory diagram showing the impurity concentration distribution of the N-type buried collector layer and the pedestal collector layer in the depth direction at the position A in FIG.

In this semiconductor device, a P-type silicon substrate 1 as a semiconductor substrate of one conductivity type, a first N-type buried collector layer 21 as a buried collector layer of a reverse conductivity type, and a second N-type buried collector layer as a collector layer of a reverse conductivity type are used. -Type buried collector layer 22, N-type silicon epitaxial layer 3, which is a reverse conductivity type collector layer, element isolation oxide film 4, N-type buried collector lead layer 5, base lead electrode 6, P-type external base layer 7, one conductivity type base A P-type intrinsic base layer 8, an insulating film 9,
Sidewall insulating film 10, emitter electrode 11, emitter diffusion layer 12, and N, which is a reverse conductivity type pedestal collector layer
The pedestal collector layer 102 is provided.

FIGS. 3 to 7 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present embodiment. First, as shown in FIG. 3, a first N-type buried collector layer 21 doped with antimony having a small diffusion coefficient is formed in a predetermined region of a P-type silicon substrate 1 to a depth L1. Next, a predetermined region where a high-frequency transistor is to be formed is doped with phosphorus ions having a large diffusion coefficient at an energy of 40 to 80 KeV, so that the second N-type buried collector layer 22 has a depth L2.
It forms until it becomes. Thereafter, an N-type silicon epitaxial layer 3 doped with phosphorus is grown to about 2 μm. In this case, the impurity concentration extends from 1.1 μm shown in FIG. 9 to 2.0 μm shown in FIG. After the formation of the N-type silicon epitaxial layer 3, the doped phosphorus diffuses into the N-type silicon epitaxial layer 3 and spreads to the region shown by the broken line in FIG. 3, and the impurity concentration becomes 2.0 as shown in FIG.
Spread over the area of μm or more.

Next, as shown in FIG. 4, about 0.3 to about 0.3 to
An element isolation oxide film 4 having a thickness of about 0.5 μm is formed.
Then, an N-type buried collector extraction layer 5 is formed. Thereafter, a polysilicon film having a thickness of about 0.2 to 0.3 μm is grown, and boron ions are implanted into the polysilicon film.
After growing an insulating film having a thickness of about 0.1 to 0.2 μm, the insulating film and the polysilicon film are etched in order,
The base extraction electrode 6 and the insulating film 9 as shown in FIG. 5 are formed.

Then, a heat treatment is performed for about 60 minutes in an atmosphere of about 900 ° C., and boron is diffused from the base lead electrode 6 into the N-type silicon epitaxial layer 3. A P-type external base layer 7 having a depth of about 0.3 μm is formed. Further, the emitter opening of the base lead-out electrode 6 is formed on the N-type silicon epitaxial layer 3 of about 0.4 μm, which is thinner than that at the time of growth by the rising of the second N-type buried collector layer 22 in the high-frequency transistor formation region. From a part, for example, phosphorus ion implantation is performed at an energy of 200 to 300 KeV,
As shown in FIG. 2, a pedestal collector layer 102 is formed in a region having a depth of 0.2 to 0.5 μm. At the same time, for example, boron ion implantation is performed at an energy of 10 to 20 KeV to selectively form the P-type intrinsic base layer 8 having a depth of about 0.2 μm.

Next, as shown in FIG.
After forming the sidewall insulating film 10 having a thickness of 25 μm, an emitter electrode 12 as shown in FIG. 1 is formed using a polysilicon film. Thereafter, for example, arsenic ion implantation is performed at an energy of 40 to 80 KeV, and after doping impurities into the emitter electrode 12, heat treatment is performed to about 0.1
By forming an emitter diffusion layer 11 having a depth of about μm,
Is completed.

On the other hand, the high-breakdown-voltage transistor formed in another part of the same semiconductor substrate is composed of the N-type second buried collector layer 22 and the N-type pedestal collector layer 1 shown in FIG.
02 can be configured by omitting the high-concentration impurity layer and making other diffusion layers the same as the high-frequency transistor.

As described above, according to the embodiment, the high-frequency transistor is formed by the second base formed immediately below the intrinsic base layer 8.
The high-concentration impurity layers of the buried collector layer 22 and the N-type pedestal collector layer 102 reduce the parasitic collector resistance from the intrinsic base layer 8 to the N-type buried collector layer 2 and also suppress the Kirk effect. In addition, a high breakdown voltage transistor can be formed in another portion of the same semiconductor substrate by sharing the diffusion process for the high-frequency transistor. If the thickness of the N-type silicon epitaxial layer 3 is increased, the high-frequency transistor The breakdown voltage of the high breakdown voltage transistor can be increased without deteriorating the characteristics.

[0019]

As described above, according to the present invention, one of the two types of impurity diffusion layers of the opposite conductivity type constituting the buried collector layer is brought into contact with the pedestal collector layer to constitute a semiconductor device. Not only the parasitic collector resistance of the transistor can be reduced, but also the Kirk effect can be suppressed. Further, by omitting the second buried collector layer and the pedestal collector layer constituting the high-frequency transistor, a high-voltage transistor can be configured. Therefore, the high-frequency transistor and the high-voltage transistor can be formed on the same substrate without increasing the number of diffusion steps. Can be configured.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a structure of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing an impurity concentration distribution of each layer including a buried collector layer and a pedestal collector layer in the semiconductor device according to the present embodiment;

FIG. 3 is a sectional view (No. 1) showing the method for manufacturing the semiconductor device in the embodiment.

FIG. 4 is a cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device in the present embodiment.

FIG. 5 is a sectional view (No. 3) showing the method for manufacturing the semiconductor device in the embodiment.

FIG. 6 is a sectional view (part 4) illustrating the method for manufacturing the semiconductor device in the embodiment;

FIG. 7 is a sectional view (No. 5) showing the method for manufacturing the semiconductor device in the present embodiment.

FIG. 8 is a cross-sectional view illustrating a structure of a conventional semiconductor device.

FIG. 9 is an explanatory diagram showing an impurity concentration distribution of a pedestal collector layer in a conventional semiconductor device.

[Explanation of symbols]

 Reference Signs List 1 P-type silicon substrate 2 N-type buried collector layer 21 First N-type buried collector layer 22 Second N-type buried collector layer 3 N-type silicon epitaxial layer 4 Element isolation oxide film 5 N-type buried collector lead layer 6 Base lead Electrode 7 P-type external base layer 8 P-type intrinsic base layer 9 Insulating film 10 Side wall insulating film 11 Emitter diffusion layer 12 Emitter electrode 102 to 104 N-type pedestal collector layer

 ──────────────────────────────────────────────────の Continuing from the front page (72) Inventor Shigeki Sawada 1-1, Komachi, Takatsuki-shi, Osaka Matsushita Electronics Co., Ltd. F-term (reference) 5F003 AP00 AP06 BA96 BB06 BB07 BB08 BC01 BC02 BC05 BC08 BE07 BE08 BF03 BG03 BP06 BP08 BP09 BP23 BP31 BP41 BS06 BS08

Claims (2)

[Claims] 1. A reverse conductivity type buried collector layer formed on a semiconductor substrate of one conductivity type, a reverse conductivity type collector layer formed on the reverse conductivity type buried collector layer, and an upper portion of the reverse conductivity type collector layer In a semiconductor device having a base layer of one conductivity type formed on the base layer, and a pedestal collector layer of a reverse conductivity type formed immediately below the base layer of the one conductivity type, the reverse conductivity type buried collector layer has two or more types. A reverse conductivity type impurity diffusion layer, and at least one of the
A semiconductor device, wherein two opposite conductivity type impurity diffusion layers are arranged at positions in contact with the opposite conductivity type pedestal collector layer. 2. A step of forming a first reverse-conductivity-type buried collector layer with a first reverse-conductivity-type impurity in a one-conductivity-type semiconductor substrate; A step of forming a collector layer; a step of forming a reverse conductivity type collector layer on the first reverse conductivity type buried collector layer and the second reverse conductivity type buried collector layer; Forming a reverse conductivity type pedestal collector layer at a position in contact with the first reverse conductivity type buried collector layer or the second reverse conductivity type buried collector layer from a predetermined opening on the surface; Forming a one-conductivity-type base layer on the reverse-conductivity-type pedestal collector layer.