KR0164521B1 - Method of fabricating bipolar transistor - Google Patents
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- KR0164521B1 KR0164521B1 KR1019950068647A KR19950068647A KR0164521B1 KR 0164521 B1 KR0164521 B1 KR 0164521B1 KR 1019950068647 A KR1019950068647 A KR 1019950068647A KR 19950068647 A KR19950068647 A KR 19950068647A KR 0164521 B1 KR0164521 B1 KR 0164521B1
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 239000000463 material Substances 0.000 claims abstract description 43
- 238000000034 method Methods 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 125000006850 spacer group Chemical group 0.000 claims abstract description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 11
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 11
- 239000010703 silicon Substances 0.000 claims abstract description 11
- 239000012535 impurity Substances 0.000 claims abstract description 9
- 239000011810 insulating material Substances 0.000 claims abstract description 8
- 239000004065 semiconductor Substances 0.000 claims abstract description 6
- 239000004020 conductor Substances 0.000 claims abstract description 5
- 239000012212 insulator Substances 0.000 claims abstract description 5
- 238000005530 etching Methods 0.000 claims description 20
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 10
- 229920005591 polysilicon Polymers 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 238000005516 engineering process Methods 0.000 abstract description 8
- 238000001020 plasma etching Methods 0.000 description 4
- 230000010354 integration Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
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- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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Abstract
신규한 바이폴라 트랜지스터의 제조방법이 개시되어 있다. 반도체기판 상에 매몰절연층 및 실리콘층을 차례로 형성하여 실리콘-온 인슐레이터(SOI) 기판을 준비한 후, 그 위에 산화막, 식각저지층 및 제1물질층을 차례로 형성한다. 제1 물질층을 식각하여 베이스영역을 정의하고 제1 도전형 불순물을 이온주입한다. 노출된 식각저지층 및 산화막을 식각한다. 제1 도전형으로 도핑된 도전물질을 침적하고 이를 에치백하여 제1 도전형 베이스전극을 형성한다. 제1 물질층을 제거한다. 절연물질을 침적하고 이를 식각하여 제1 도전형 베이스전극의 측벽에 절연성 스페이서를 형성한다. 제2 도전형 불순물을 이온주입하여, 제1 도전형 베이스전극에 셀프-얼라인되는 제2 도전형 에미터 및 콜렉터를 형성한다. SOI 기술을 사용하는 CMOS 공정에 쉽게 삽입할 수 있으므로, 고속·저소비 전력·고집적의 BiCMOS 소자를 구현할 수 있다.A novel method of manufacturing a bipolar transistor is disclosed. A buried insulating layer and a silicon layer are sequentially formed on the semiconductor substrate to prepare a silicon-on-insulator (SOI) substrate, and then an oxide film, an etch stop layer, and a first material layer are sequentially formed thereon. The first material layer is etched to define a base region and ion implanted first conductivity type impurities. The exposed etch stop layer and the oxide film are etched. A conductive material doped with a first conductivity type is deposited and etched back to form a first conductivity type base electrode. The first material layer is removed. An insulating material is deposited and etched to form an insulating spacer on the sidewall of the first conductivity type base electrode. The second conductivity type impurities are implanted to form a second conductivity type emitter and a collector which are self-aligned to the first conductivity type base electrode. It can be easily inserted into CMOS processes using SOI technology, enabling high-speed, low-power consumption, and highly integrated BiCMOS devices.
Description
제1도는 본 발명에 의한 SOI 구조의 횡형 NPN 바이폴라 트랜지스터의 평면도.1 is a plan view of a lateral NPN bipolar transistor having an SOI structure according to the present invention.
제2도는 내지 제5도는 본 발명에 의한 SOI 구조의 횡형 NPN 바이폴라 트랜지스터의 제조방법을 설명하기 위한 단면도들.2 to 5 are cross-sectional views illustrating a method of manufacturing a lateral NPN bipolar transistor having an SOI structure according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : SOI 기판 2 : 산화막1: SOI Substrate 2: Oxide Film
3 : 식각저지층 4 : 제1 물질층3: etch stop layer 4: first material layer
5 : 제1 측벽스페이서 6 : 폴리실리콘층5: first sidewall spacer 6: polysilicon layer
7 : 제2 측벽스페이서7: second sidewall spacer
본 발명은 반도체장치의 제조방법에 관한 것으로, 특히 실리콘-온 인슐레이터(Silicon On Lnsulator; 이하 SOI라 한다) 구조를 갖는 횡형(lateral) NPN 바이폴라 트랜지스터의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a lateral NPN bipolar transistor having a silicon on insulator (SOI) structure.
반도체장치의 집적도가 256Mb급 이상으로 고집접화됨에 따라, SOI 웨이퍼 상에 소자들을 형성하기 위한 노력들이 광범위하게 이루어지고 있다. SOI는 보다 효과적으로 실리콘기판 상에 형성되는 반도체 소자들을 상호 분리하는 기술로서, 접합 분리(Junction Isolation) 기술보다 빛에 강하고 높은 공급전압에 강한 특성을 나타낸다. 또한 일반적으로, 벌크 실리콘 상에 형성된 소자보다 SOI 상에 형성된 소자가 결과적으로 요구하는 공정수가 작으며, IC칩 내에 형성된 소자들간에 나타나는 용량성 결합(capacitive coupling)이 줄어드는 잇점이 있다. 이러한 소자를 SOI 소자라고 하는데, SOI 소자는 문턱 기울기(Threshold slope)가 크며, 2V까지 저전압하는 경우에도 특성의 저하가 별로없는 장점을 가진다. 또한, 소자열화를 유발하기 어려운 구조로 제작할 수 있기 때문에 높은 수율도 기대할 수 있다. 특히, 박막의 SOI 소자는 소자의 특성을 개선시키기 위한 별도의 웰(well) 형성공정이 없기 때문에, 기존의 벌크 실리콘기판 상에 형성되는 소자에 비해 공정이 감소된다. 이러한 SOI 기술은 웰이 형성되지 않으므로 주로 기판의 표면에서 동작하는 CMOS용 공정으로 사용된다.As the integration density of semiconductor devices is higher than 256 Mb, efforts have been made to form devices on SOI wafers. SOI is a technology for more effectively separating semiconductor devices formed on a silicon substrate, and is more resistant to light and more resistant to high supply voltage than Junction Isolation. Also, in general, the number of processes required by the device formed on the SOI is smaller than the device formed on the bulk silicon, and the capacitive coupling between devices formed in the IC chip is reduced. Such a device is referred to as an SOI device, and the SOI device has a large threshold slope, and even when the voltage is lowered to 2V, there is little deterioration in characteristics. In addition, high yields can also be expected because it can be fabricated in a structure that is difficult to cause device degradation. In particular, since the thin SOI device does not have a separate well forming process for improving the characteristics of the device, the process is reduced compared to a device formed on a conventional bulk silicon substrate. This SOI technology is mainly used as a process for CMOS that operates on the surface of a substrate since no well is formed.
한편, CMOS 트랜지스터와 바이폴라 트랜지스터를 하나의 칩 내에 내장하는 BiCMOS 기술을 사용한, 고속·저소비 전력·고집적의 BiCMOS 메모리제품이 현재 널리 사용되고 있다. 이러한 BiCMOS 기술에는 CMOS 트랜지스터의 저소비 전력·고집적 특성과 바이폴라 트랜지스터의 고속 스위칭 특성·고전류 구동능력을 모두 이용할 수 있다. 이에 따라, CMOS 트랜지스터의 제조공정과 양립할 수 있으면서 고속 스위칭 특성 및 고저류 구동능력을 갖는 바이폴라 트랜지스터를 형성할 수 있는 제조방법의 최적화가 절실히 요구되고 있다.On the other hand, high speed, low power consumption, and high density BiCMOS memory products using BiCMOS technology in which CMOS transistors and bipolar transistors are embedded in one chip are widely used. Such BiCMOS technology can utilize both the low power consumption and high integration characteristics of CMOS transistors, the high speed switching characteristics and high current driving capability of bipolar transistors. Accordingly, there is an urgent need for an optimization of a manufacturing method capable of forming a bipolar transistor having high speed switching characteristics and high low current driving capability while being compatible with a manufacturing process of a CMOS transistor.
따라서, 본 발명의 목적은 SOI 기술을 기존의 CMOS 공정에 손쉽게 삽입하여 횡형으로 NPN 바이폴라 트랜지스터를 형성함으로써 고속·저소비 전력·고집적의 BiCMOS 소자를 구현할 수 있는 바이폴라 트랜지스터의 제조방법을 제공하는데 있다.Accordingly, an object of the present invention is to provide a method for manufacturing a bipolar transistor that can implement a high-speed, low power consumption, high-integration BiCMOS device by easily inserting SOI technology into an existing CMOS process to form an NPN bipolar transistor horizontally.
상기 목적을 달성하기 위하여 본 발명은,The present invention to achieve the above object,
반도체기판 상에 매몰절연층 및 실리콘층을 차례로 형성하여 실리콘-온 이슐레이터(SOI) 기판을 준비하는 단계;Preparing a silicon-on isolator (SOI) substrate by sequentially forming a buried insulating layer and a silicon layer on the semiconductor substrate;
상기 실리콘-온-인슐레이터 기판 상에 산화막, 식각저지층 및 제1 물질층을 차례로 형성하는 단계;Sequentially forming an oxide film, an etch stop layer, and a first material layer on the silicon-on-insulator substrate;
상기 제1 물질층을 식각하여 베이스영역을 정의하고, 상기 베이스영역에 제1 도전형의 불순물을 이온주입하는 단계;Etching the first material layer to define a base region, and implanting impurities of a first conductivity type into the base region;
상기 노출된 식각저지층 및 산화막을 식각하는 단계;Etching the exposed etch stop layer and the oxide film;
상기 결과물 상에 제1 도전형으로 도핑된 도전물질을 침적하고 이를 에치백하여 제1 도전형의 베이스전극을 형성하는 단계;Depositing a conductive material doped with a first conductive type on the resultant material and etching back the conductive material to form a first conductive base electrode;
상기 제1 물질층을 제거하는 단계;Removing the first material layer;
상기 결과물 상에 절연물질을 침적하고 이를 식각하여 상기 제1 도전형의 베이스전극 측벽에 절연성 스페이서를 형성하는 단계; 및Depositing an insulating material on the resultant and etching the insulating material to form insulating spacers on sidewalls of the first conductive base electrode; And
상기 결과물에 제2 도전형의 불순물을 이온주입하여, 상기 제1 도전형의 베이스전극에 셀프-얼라인되는 제2 도전형의 에미터 및 콜렉터를 형성하는 단계를 구비하는 것을 특징으로 하는 바이폴라 트랜지스터의 제조방법을 제공한다.And ion-implanting a second conductivity type impurity into the resultant to form a second conductivity type emitter and a collector self-aligned to the first conductivity type base electrode. It provides a method of manufacturing.
상기 식각저지층을 구성하는 물질로 폴리실리콘을 사용하고 상기 제1 물질층을 구성하는 물질로 저온산화물을 사용하는 것이 바람직하다.It is preferable to use polysilicon as the material constituting the etch stop layer and to use a low temperature oxide as the material constituting the first material layer.
상기 노출된 식각저지층 및 산화막을 식각하는 단계 전에, 상기 식각된 제1 물질층의 측벽에 제2 물질층으로 이루어진 측벽스페이서를 형성하는 단계를 더 구비할 수 있다. 상기 제2 물질층을 구성하는 물지로 실리콘질화물을 사용하는 것이 바람직하다. 상기 제2 물질층으로 이루어진 측벽스페이서는 상기 제1 물질층을 제거하는 단계에서 함께 제거하는 것이 바람직하다.Before etching the exposed etch stop layer and the oxide layer, the method may further include forming a sidewall spacer formed of a second material layer on sidewalls of the etched first material layer. It is preferable to use silicon nitride as the material constituting the second material layer. Preferably, the sidewall spacers formed of the second material layer are removed together in the step of removing the first material layer.
상기 절연성 스페이서를 형성하기 위한 식각공정시 상기 식각저지층이 함께 식각된다.In the etching process for forming the insulating spacer, the etch stop layer is etched together.
본 발명에 의한 바이폴라 트랜지스터의 제조방법은 SOI 기술을 사용하는 CMOS 공정에 쉽게 삽입할 수 있으므로, 고속·저소비 전력·고집적의 BiCMOS 소자를 구현할 수 있다.Since the method for manufacturing a bipolar transistor according to the present invention can be easily inserted into a CMOS process using SOI technology, it is possible to realize a high speed, low power consumption, and high density BiCMOS device.
이하, 본 발명의 바람직한 실시예를 첨부한 도면을 참조하여 상세히 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
제1도는 본 발명에 의한 SOI 구조의 횡형 NPN 바이폴라 트랜지스터의 평면도이다.1 is a plan view of a lateral NPN bipolar transistor having an SOI structure according to the present invention.
제1도를 참조하면, 본 발명에서는 SOI 기판 상에 바이폴라 트랜지스터를 형성하기 때문에 NPN 바이폴라 트랜지스터를 횡형으로 형성할 수 있다 (기존에는 NPN 바이폴라 트랜지스터를 수직으로만 형성할 수 있었다). 따라서, P+폴리실리콘으로 형성되는 베이스영역에 셀프-얼라인되도록 N+에미터 및 콜렉터 영역을 형성할 수 있다. 또한, P+베이스의 콘택(10)을 따로 뽑아내어 형성하기 때문에, 에미터 및 콜렉터 콘택(11,12)과의 디자인-룰에 구애되지 않아 레이아웃 측면에서 매우 유리하다.Referring to FIG. 1, in the present invention, since the bipolar transistor is formed on the SOI substrate, the NPN bipolar transistor can be formed horizontally (in the past, the NPN bipolar transistor could be formed only vertically). Therefore, the N + emitter and collector regions can be formed to self-align to the base region formed of P + polysilicon. In addition, since the contact 10 of the P + base is drawn out separately, it is very advantageous in terms of layout because it is not bound to design rules with the emitter and collector contacts 11 and 12.
제2도 내지 제5도는 본 발명에 의한 SOI 구조의 횡형 NPN 바이폴라 트랜지스터의 제조방법을 설명하기 위한 단면도들이다.2 to 5 are cross-sectional views illustrating a method of manufacturing a lateral NPN bipolar transistor having an SOI structure according to the present invention.
제2도는 베이스영역을 정의하는 단계를 도시한다. 실리콘기판(도시되지 않음)을 준비한 후, 상기 기판 상에 SiO2로 이루어진 매몰절연층(도시되지 않음)을 형성한다. 이어서, 상기 매몰절연층 상에 1500∼2000Å 정도의 두께로 실리콘층을 성장시킨다. 이때, 상기 실리콘층은 약하게 도핑된 N형으로 형성된다. 상기한 공정의 결과로 SOI 기판(1)이 완성된다. 상기 SOI 기판(1)은 통상적인 SOI 기술, 예컨대 SIMOX(Seperation by Implanted Oxygen) 등의 기술로 형성할 수 있다. 다음에, 사진식각 공정을 통해 상기 SOI 기판을 식각하여, 활성영역에 실리콘섬(silicon islands)을 만든 후, CMOS 소자가 형성될 활성영역에 N형 또는 P형 불순물을 이온주입하여 N-채널 및 P-채널을 각각 형성한다. 이어서, 상기 결과물 전면에 열산화 방법으로 산화막(2)을 100∼200Å 정도의 두께로 형성한다. 상기 산화막(2)은 CMOS 소자에서 게이트산화막의 역할을 한다. 계속해서, 상기 산화막(2) 상에 식각저지층(3), 예컨대 폴리실리콘을 약 500Å의 두께로 침적한 후, 그 위에 제1 물질층(4), 예컨대 저온산화물(low temperature oxide; LTO)을 약 4000Å 두께로 침적한다. 여기서, 상기 제1 물질층(4)을 구성하는 물질은 임의의 식각공정에 대해 상기 식각저지층(3)을 구성하는 물질과는 좋은 식각선택비를 갖는 것이 바람직하다. 이어서, 사진식각 공정으로 상기 제1 물질층(4)을 식각하여 베이스영역을 정의한 후, 상기 정의된 베이스영역에 P형 불순물, 예컨대 보론을 이온주입한다. 상기한 이온주입에 의해 P형 고유베이스 영역이 형성된다.2 shows a step of defining a base area. After preparing a silicon substrate (not shown), a buried insulating layer (not shown) made of SiO 2 is formed on the substrate. Subsequently, a silicon layer is grown on the buried insulating layer to a thickness of about 1500 to 2000 GPa. At this time, the silicon layer is formed of a lightly doped N-type. As a result of the above process, the SOI substrate 1 is completed. The SOI substrate 1 may be formed by a conventional SOI technique such as Separation by Implanted Oxygen (SIMOX). Next, the SOI substrate is etched through a photolithography process, silicon islands are formed in an active region, and N-type and P-type impurities are ion implanted into the active region where a CMOS device is to be formed. Each of the P-channels is formed. Subsequently, an oxide film 2 is formed on the entire surface of the resultant with a thickness of about 100 to 200 kPa by a thermal oxidation method. The oxide film 2 serves as a gate oxide film in a CMOS device. Subsequently, an etch stop layer 3, such as polysilicon, is deposited on the oxide film 2 to a thickness of about 500 GPa, and thereafter, the first material layer 4, for example, low temperature oxide (LTO), is deposited thereon. To about 4000 mm thick. Here, the material constituting the first material layer 4 preferably has a good etching selectivity with respect to the material constituting the etch stop layer 3 for any etching process. Subsequently, the first material layer 4 is etched by a photolithography process to define a base region, and then P-type impurities such as boron are implanted into the defined base region. The p-type native base region is formed by the above ion implantation.
제3도는 제1 측벽스페이서를 형성하는 단계를 도시한다. 상기 결과물 상에, 임의의 습식식각 공정에 대해 상기 식각저지층(3)을 구성하는 물질과는 좋은 식각선택비를 갖고 상기 제1 물질층(4)을 구성하는 물질과는 비슷한 식각율을 갖는 제2 물질층, 예컨대 실리콘질화물(Si3N4)을 약 1000Å 두께로 침적한 후, 이를 바응성이온식각(reactive ion etching; 이하 RIE라 한다) 방법으로 식각하여 상기 식각된 제1 물질층(4)의 측벽에 제2 물질층으로 이루어진 제1 측벽스페이서(5)를 형성한다. 상기 제1 측벽스페이서(5)는 후속공정에서 형성될 P+베이스 폴리실리콘전극이 그 양쪽에 형성되는 에미터나 콜렉터 쪽으로 외확산(out-diffusion)되어 단락되는 것을 방지하는 역할을 한다. 상기 제1 측벽스페이서(5)를 형성하는 단계를 생략할 수 있음은 물론이다.3 illustrates forming a first sidewall spacer. On the resultant, for any wet etching process, the material constituting the etch stop layer 3 has a good etching selectivity and an etching rate similar to that of the material constituting the first material layer 4. After depositing a second material layer, for example, silicon nitride (Si 3 N 4 ) to a thickness of about 1000 Å, the second material layer is etched by reactive ion etching (hereinafter referred to as RIE) method to form the etched first material layer ( A first sidewall spacer 5 consisting of a second layer of material is formed on the sidewall of 4). The first sidewall spacer 5 serves to prevent the P + base polysilicon electrode to be formed in a subsequent process from being short-circuited out-diffusion toward the emitter or collector formed on both sides. Of course, the step of forming the first sidewall spacer 5 may be omitted.
제4도는 P+베이스전극(6)을 형성하는 단계를 도시한다. 상기 제1 측벽스페이서(5)를 식각마스크로 사용하여 노출된 상기 식각저지층(3) 및 산화막(2)을 습식식각한 후, 결과물 전면에 P+로 도핑된 폴리실리콘을 침적한다. 이어서, 상기 P+폴리실리콘층을 에치백(etch-back)하여 P+베이스 전극(6)을 형성한다.4 shows the step of forming the P + base electrode 6. After wet etching the exposed etch stop layer 3 and the oxide film 2 using the first sidewall spacer 5 as an etch mask, polysilicon doped with P + is deposited on the entire surface of the resultant. Subsequently, the P + polysilicon layer is etched back to form the P + base electrode 6.
제5도는 N+에미터(8) 및 N+콜렉터(9)를 형성하는 단계를 도시한다. 상기 제1 물질층(4) 및 제1 측벽스페이서(5)를 제거한 후, 결과물 전면에 절연물질, 예컨대 저온산화물(LTO)을 약 1500Å 두께로 침적한다. 이어서, 상기 절연물질층을 식각대상물로 하면서 상기 500Å 두께로 형성된 식각저지층(3)을 함께 식각할 수 있는 조건으로 RIE 식각을 실시하여, 상기 P+베이스전극(6)의 측벽에 절연물질(LTO)로 이루어진 제2 측벽스페이서(7)를 형성한다. 다음에, 상기 RIE 식각공정에 의해 손상되었을 상기 산화막 (게이트산화막)(2)을 큐어링하기 위해 열산화 공정을 실시한 후, 상기 P+베이스전극(6)을 이온주입방지 마스크로 사용하여 N형 불순물, 예컨대 비소(As)를 높은 도즈로 이온주입하여 N+에미터(8) 및 N+콜렉터(9)를 형성한다. 이어서, 도시하지는 않았으나, 통상적인 금속배선 공정을 실시하여 상기 N+에미터(8) 및 N+콜렉터(9)상에 각각 전극들을 형성하여 횡형 NPN 바이폴라 트랜지스터를 완성한다.5 shows the steps of forming an N + emitter 8 and an N + collector 9. After the first material layer 4 and the first sidewall spacer 5 are removed, an insulating material, such as low temperature oxide (LTO), is deposited on the entire surface of the resultant to a thickness of about 1500 kPa. Subsequently, RIE etching is performed under the condition that the insulating material layer is an etch target, and the etching stop layer 3 formed to the thickness of 500 Å can be etched together to form an insulating material on the sidewalls of the P + base electrode 6. A second sidewall spacer 7 made of LTO is formed. Next, after performing a thermal oxidation process to cure the oxide film (gate oxide film) 2 that would have been damaged by the RIE etching process, the P + base electrode 6 was used as an ion implantation prevention mask. Impurities such as arsenic (As) are ion implanted at high doses to form N + emitter 8 and N + collector 9. Subsequently, although not shown, a conventional metallization process is performed to form electrodes on the N + emitter 8 and the N + collector 9 to complete a lateral NPN bipolar transistor.
이상 상술한 바와 같이 본 발명에 횡형 NPN 바이폴라 트랜지스터의 제조방법에 의하면, 다음과 같은 효과들을 얻을 수 있다.As described above, according to the method of manufacturing the lateral NPN bipolar transistor according to the present invention, the following effects can be obtained.
첫째, SOI 기판 상에 횡형으로 베이스, 에키터 및 콜렉터를 형성하기 때문에, P+베이스에 셀프-얼라인되도록 N+에미터 및 콜렉터를 형성하는 것이 가능하다.Firstly, since the base, the emitter and the collector are formed on the SOI substrate laterally, it is possible to form the N + emitter and the collector to self-align to the P + base.
둘째, 고유베이스 영역의 바로 위에 P+폴리실리콘 베이스를 형성하기 때문에 베이스영역의 저항이 감소된다.Second, since the P + polysilicon base is formed directly above the intrinsic base region, the resistance of the base region is reduced.
셋째, SOI 기술을 사용하는 CMOS 공정에 쉽게 삽입하여 BiCMOS 공정을 구현할 수 있다.Third, the BiCMOS process can be easily inserted into a CMOS process using SOI technology.
넷째, P+폴리실리콘 베이스의 콘택을 별도로 뽑아내어 형성하기 때문에, 상기 베이스 콘택이 에미터나 콜렉터 콘택과의 디자인 룰에 구애되지 않아 레이아웃 측면에서 매우 유리하다.Fourth, since the contact of the P + polysilicon base is separately formed, the base contact is not advantageous to the design rule with the emitter or the collector contact, which is very advantageous in terms of layout.
본 발명이 상기 실시예에 한정되지 않으며, 많은 변형이 본 발명의 기술적 사상내에서 당분야에서 통상의 지식을 가진 자에 의하여 가능함은 명백하다.The present invention is not limited to the above embodiments, and it is apparent that many modifications are possible by those skilled in the art within the technical idea of the present invention.
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| KR100413751B1 (en) * | 2000-10-20 | 2004-01-03 | 인터내셔널 비지네스 머신즈 코포레이션 | FULLY-DEPLETED-COLLECTOR SILICON-ON-INSULATOR(SOI) BIPOLAR TRANSISTOR USEFUL ALONE OR IN SOI BiCMOS |
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