JPH01289162A - Bipolar transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To exclude smoothly excessive carriers from a highly implanted region and to make possible a high-speed switching action by a method wherein a base region and an emitter region are made to selfalign and the emitter and base high-concentration regions are completely isolated from each other. CONSTITUTION:A wafer, in which an n-type epitaxial layer 103 is formed on a P-type Si substrate 101 through an n<+> buried layer 102, is used to form an emitter sidewall insulating film 115. Then, the surfaces of poly Si films 110 and 113 are oxidized to form emitter and base electrode isolation insulating films 117. Boron is diffused in the substrate from the films 113 for external bases by the heat treatment at this time and the heat treatment at the time of formation of the film 115, and P<+> external base regions 116 are formed. After that, a nitride film 107 is removed to form an internal base layer 118, a poly Si film 119 is deposited and etched, an oxide film 106 is removed using the film 119 as a mask to deposit a poly Si film 120 and an emitter layer 121 is formed. Accordingly, the layers 116, 115 and 121 are formed by self-alignment and the layers 121 and 116 are isolated from each other.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention 1 (Industrial Application Field) The present invention relates to a method for manufacturing a high-performance bipolar transistor in which a base region and an emitter region are formed in a self-aligned manner.

(Prior Technology) High-performance silicon bipolar transistors are used not only as components for digital circuits such as processors and memories for high-speed calculations used in computers, but also as elements for analog circuits such as operational amplifiers and comparators, and for digital/analog devices. It is also widely used as a mixed DA/AD converter. Recently, several methods have been proposed for forming a base region and an emitter region of a high-performance bipolar transistor using self-alignment technology. Typical conventional techniques will be described here, and their problems will be clarified.

FIGS. 4(a) to 4(d) show the manufacturing process of a conventional example. A wafer is used in which an n-type layer 203 serving as a collector layer is epitaxially grown on a p-type 3i substrate 201 via an n-type buried layer 202.

For device isolation on this wafer, n is used as a channel stopper.
A mold layer 204 is formed, and an oxide film 20 is formed by selective oxidation.
5 is formed. After forming a thin oxide layer 11206 on the entire surface of the element region of this wafer, a silicon nitride film 207, which is an oxidation-resistant film, is deposited on the entire surface, and then a first polycrystalline silicon film 208 is deposited. First polycrystalline silicon 1120
8, unnecessary portions of the element isolation region are converted into an oxide film 209 by thermal oxidation. Next, the first polycrystalline silicon film 20
Boron is added to 8 by ion implantation, and the first polycrystalline silicon 1 on the emitter formation region is etched by photoetching.
Etch I208 to provide an opening (Fig. 4(a)
). Thereafter, oxidation is performed to form oxide 11!210 on the surface of the polycrystalline silicon, and using this oxide film 210 as a mask, the silicon nitride 1207 in the opening is removed by etching with a heated aqueous phosphoric acid solution. And exposed oxidation! 1206 is removed by etching with an ammonia fluoride aqueous solution to expose the wafer surface. At this time, by intentionally over-etching the silicon nitride film 207 at the opening, a knee-bar hang portion 211 is formed,
A portion of the first polycrystalline silicon film 208 is exposed (
Figure 4(b)). Then second polycrystalline silicon M 21
2 is stacked on the entire surface by H1 to fill the hollow part under the overhang part 211, and the polycrystalline silicon I!
1212 is etched to expose the oxidized 1210 and the wafer surface of the opening (FIG. 4(C)). Subsequently, a thermal oxide film 213 is formed on the exposed wafer surface and side surfaces of the polycrystalline silicon film. At this time, the first polycrystalline silicon llI208 was doped with boron,
A p-type external base layer 214 is formed by diffusing into the wafer through the second polycrystalline silicon film 212 in the overhang portion. Thereafter, a p-type internal base layer 215 is formed by boron ion implantation. Next, CVD insulation! 11
216 and third polycrystalline silicon 11217 are sequentially stacked, and etched by anisotropic etching, leaving only the side walls of the opening, and the remaining third polycrystalline silicon 1!217 is used as an etching mask to form the opening. Remove the oxide film on the surface of the wafer. Then, a fourth polycrystalline silicon film 218 doped with arsenic at a high concentration is deposited, and the arsenic is diffused by heat treatment to form an emitter 1219 (FIG. 4(d)).

The first and second polycrystalline silicon films 208 and 212 are used as base electrodes, and the fourth polycrystalline silicon film 218 is used as an emitter electrode.

According to this method, the emitter base is formed in a self-aligned manner, and the emitter diffusion opening is ~0.35 μm.
The emitter opening to the base opening is 0.25 μm, and the base opening is 0.35 μm, making it possible to create a very fine structure. However, in a bipolar transistor formed by such a method, the high concentration layers of the p medium type external base region and the n medium type emitter region are likely to be formed close to each other in the lateral direction. As a result, the withstand voltage of the emitter-base junction decreases, or the parasitic capacitance (1) becomes extremely large. On the other hand, if a sufficient space is left between the emitter layer and the external base layer in order to eliminate this problem, the base resistance will increase.

(Problem to be solved by the invention) As described above, in conventional high-performance self-aligned bipolar transistors, it is extremely difficult to optimally design the emitter-base distance to a small value, and high-speed switching is difficult. However, problems remain.

SUMMARY OF THE INVENTION The present invention provides a bipolar transistor that solves these problems and a method for manufacturing the same. An emitter 13i1 wall insulating film is embedded in the substrate deeper than the junction surface of the internal base and the collector at the tip of the insulating film for the purpose of the emitter, and the internal base layer and the emitter barrier insulating film are surrounded by the emitter barrier insulating film. The present invention is characterized in that an emitter layer is formed, and an external base layer is formed from the bottom of the emitter barrier insulating film to the outside.

In the method of the present invention, first, a first insulating film, an oxidation-resistant film, and a second insulating film are sequentially formed on a semiconductor wafer having a collector layer of a first conductivity type, and then a second insulating film, an oxidation-resistant film, and a second insulating film are formed. The electrostatic film is patterned and left in the region including the emitter formation region. Next, a third insulating film and a first conductive film that will become a part of the base electrode are sequentially formed on the entire surface, and a mask material film is embedded in the recesses on the surface of the first conductive film. Etching the conductor film. Further, using the mask material film, the patterned oxidation-resistant film, and the third insulating film formed on the sidewalls of the 1Ii1 oxidation film as an etching mask,
The third and first insulating films are etched to form a first opening for forming an external base layer in a region sandwiched between the third insulating film and the mask material film left on the sidewall of the second insulating film. do.

Thereafter, the mask material film is removed by etching, and a second conductor film, which will become a part of the base electrode, is selectively embedded in the first opening.

Then, using the second conductive film and the oxidation-resistant film as a mask, the third
- Etching the first insulating film to form a second opening exposing the substrate in a region where an emitter sidewall insulating film is to be formed. Oxygen ions are implanted into this second opening region and heat treatment is applied to form an emitter sidewall insulating film made of SiO2.

A thermal oxide film is formed on the surface of the conductor film made up of the first conductor film and the second conductor film. At the same time, an impurity doped in the second conductor film in advance is diffused into the collector layer to form an external base layer of the second conductivity type. Furthermore, after removing the oxidation-resistant film and forming a third opening for forming an internal base, the third opening wAiii! The surface of the wafer is doped with impurities to form an internal base layer of a second conductivity type. Subsequently, the wafer surface in the third opening wA area where the internal base layer is formed is exposed, a third conductive film that becomes a part of the emitter electrode is formed, and impurities are removed from the wafer through the third conductive film. An emitter layer of the first conductivity type is formed by diffusing the phosphor and the like to form a first conductivity type emitter layer.

(Function) According to the structure and method of the present invention, the base region and the emitter region are self-aligned, and the high concentration regions of the base and emitter are completely separated by the emitter side wall insulation.

Therefore, no junction is formed between the highly doped external base and the emitter, and therefore the distance between the emitter and the external base can be shortened without lowering the emitter-base breakdown voltage. This makes it possible to smoothly discharge excess carriers in the high injection region,
High-speed switching operation is possible.

(Example) The present invention will be explained in detail below.

FIG. 1 shows an embodiment of a bipolar transistor, and FIGS. 2(a) to 2(h) show its manufacturing process. In this embodiment, as shown in the figure, a wafer is used in which an n-type epitaxial layer 103 serving as a collector layer is formed on a p-type Si substrate 101 via an n-type embedding 1102.

Grooves are first formed in the isolation regions of the element am region, emitter/base region, and collector/contact region of such a wafer, and oxidation 111104 for element isolation and oxidation for electrode interlayer are applied to these grooves by selective oxidation. A film 105 is formed. A silicon oxide film 106 of about 500 layers is formed by thermal oxidation as a first insulating film in the element region of the wafer separated into elements in this way, and then a silicon oxide film 106 of about 100 layers is formed as an oxidation-resistant film.
500 layers of silicon nitride F1107 are deposited by LPCVD, and on top of this, about 100 layers of silicon oxide 1108 are deposited as a second insulating film by atmospheric pressure CVD (FIG. 2(a)). Next, a CVD oxide film 108 is formed as an emitter by photoetching. 4 [Patterning is performed so as to remain in the fIR region including [], and the CVD
Using the Pli film 108 as a mask, the underlying nitride F1107
is patterned to form a third insulating film on the entire surface.
A silicon oxide film 109 with a thickness of approximately 400 mm was deposited by atmospheric pressure CVD, and then a silicon oxide film 109 with a thickness of approximately 400 mm was deposited as a first conductive film that would become a part of the base electrode.
A polycrystalline silicon film 110 is deposited by LPCVD (FIG. 2(b)). Next, a photoresist 111 is applied and etched back by plasma etching to fill in the recesses on the surface (FIG. 2(C)).

Using this photoresist 111 as an etching mask, polycrystalline silicon 111110 is etched,
CVD oxidation of the top and sides of CVD oxidation 1a108
Once 1109 is exposed, use it as an etching mask to etch the polycrystalline silicon 1110 until the underlying oxide M109 is exposed, and then roughly remove the underlying oxide film 109.
, 106 are also etched, and the photoresist 111 is formed.
A first opening 112 is formed in a region sandwiched between the oxide film 108 and the oxide layer 11109 on the side thereof (FIG. 2(d)).
). After that, the photoresist 111 is removed by ashing,
A second polycrystalline silicon film 113, which will also become part of the base electrode, is deposited by LPCVD and etched back using plasma etching to fill the first opening 112 (FIG. 2(e)). . Furthermore, by ion implantation, these first and second polycrystalline silicon I! A base electrode can be formed by doping 1110.113 with boron.

Next, using a photoresist (not shown) with an opening in the element region as an etching mask, CVD of the emitter region is performed.
The oxide films 108, 109 and 106 are etched to form a second opening 114 around the emitter formation region. Then, by implanting oxygen ions into the substrate exposed to the second gate 114 and performing heat treatment, the emitter side wall insulation #l made of SiO2 is formed! 115 is formed. The buried depth of this insulating film 115 is set to be deeper than the internal base-collector junction surface that will be formed later. The conditions for oxygen ion implantation depend on the depth of the emitter sidewall that you want to create, but for example, if you implant ions at an acceleration voltage of about 3 Q key, ~
It is possible to form an emitter sidewall insulator of about 600 emitters (FIG. 2(f)).

Next, first and second polycrystalline silicon films 110.1
By oxidizing the surface of 13, an oxide film 117 is formed which will serve as an emitter-base electrode separation insulating film. In addition,
Due to the heat treatment at this time and the heat treatment during the formation of the emitter sidewall insulating film 115, boron is diffused from the polycrystalline silicon 1113 for the external base doped with boron into the substrate, thereby causing the p-type external base region 116 to diffuse into the substrate. is formed. (Figure 2 (g)). Then nitriding! 11107 is removed using plasma etching, boron ions as an internal base impurity are implanted to form an internal base layer 118, and then a third polycrystalline silicon film 119 is deposited and etched by anisotropic etching. The third polycrystalline silicon 1179 is used as an etching mask to remove the oxide film 106 and form a fourth polycrystalline silicon film 1179.
120 is deposited by LPCVD, doped with arsenic using ion implantation, and subjected to heat treatment to form an emitter and ivy layer 121 (FIG. 2(h)).

As described above, the external base layer and emitter sidewall insulating film are formed.
A bipolar transistor in which the emitter diffusion layer is formed by self-alignment is formed.According to this embodiment, since the sidewall insulating film 115 surrounding the emitter layer 121 is embedded, the emitter layer 121 with an n medium concentration and type 1 external base layer 116 (especially p of the base electrode extraction part)
+ regions are not formed adjacent to each other, and a part of the medium-p external base layer 116 wraps around from the bottom of the sidewall insulator 1115 and extends below the left and right ends of the emitter layer 121, increasing the base resistance. It can be lowered. As a result, it has become possible to reduce the base resistance without reducing the withstand voltage of the emitter and base. At the same time, the junction capacitance between the emitter and base layers can also be kept very low. In the bipolar transistor manufactured in this way, for example, when considering the collector current dependence of the cutoff frequency < f T ), which is a main parameter of the bipolar transistor, a low injection tI4iii! Now, let's take a high-quality one because the junction capacitance between the emitter and base is low.
In the high injection region, excess charge in the emitter can be easily discharged, so a high T can be obtained.

FIG. 3 shows a bipolar transistor according to another embodiment.

Portions corresponding to those in FIG. 1 are designated by the same reference numerals and detailed explanations will be omitted. In the previous embodiment, after forming the internal base layer 118,
Whereas the emitter layer 121 was formed by narrowing the opening,
In this embodiment, the internal base layer and emitter layer are formed through the same opening. That is, the emitter width is determined by the emitter sidewall insulating film 115.

In this embodiment, since the emitter junction surface remains flat and the surrounding side wall insulation 1i11115 is n1M, there is no corner where the electric field tends to concentrate on the emitter, and the emitter
Improves base-to-base breakdown voltage.

[Effects of the Invention] As described above, according to the present invention, it is possible to realize a bipolar transistor with improved performance by embedding a sidewall insulating film around the emitter layer.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a bipolar transistor according to one embodiment of the present invention, FIGS. 2(a) to (h) are sectional views of the process, and FIG. 3 is a diagram showing a bipolar transistor according to another embodiment. 4(a) to (d) show cross-sectional views of the manufacturing process of a conventional bipolar transistor. 101...p-type 3i substrate, 102...n-type buried layer, 103...n type epitaxial layer (collector l!
2) 104.105,106...silicon oxide film, 1
07...Silicon nitride film, 108.109...CV
D silicon oxide film, 110.113... polycrystalline silicon film, 711... photoresist, 112... first
opening, 114... second opening, 115... emitter side wall insulating film, 116... external base layer, 117...
・Silicon oxide film, 118...Internal base layer, 120
...Emitter polycrystalline silicon film, 121...Emitter layer. Applicant's agent Patent attorney Takehiko Suzue Figure 2 Figure 2

Claims (2)

[Claims] (1) In a bipolar transistor with a planar structure in which an internal base layer and an external base layer are formed on the surface of the collector layer, and an emitter layer is formed on the surface of the internal base layer,
The insulating film for isolation between the emitter and base electrodes has an insulating film buried in the substrate deeper than the bonding surface between the internal base layer and the collector layer so as to surround the emitter layer at the tip of the insulating film for separating the emitter and base electrodes. bipolar transistor. (2) Depositing a first insulating film, an oxidation-resistant film, and a second insulating film in this order on a semiconductor wafer having a collector layer of a first conductivity type, and depositing the second insulating film in an emitter formation region. The oxidation-resistant film is patterned using the remaining second insulating film as an etching mask, and the third insulating film is deposited on the entire surface of the wafer. a step of depositing a first conductor film that will become a part of an electrode; a step of embedding a mask material film in a recess on the surface of the first conductor film; a step of depositing a mask material film, the patterned oxidation-resistant film, and Using the third insulating film formed on the sidewall of this oxidation-resistant film as an etching mask, the first conductive film, the third and first insulating film are
etching the insulating film to form a first opening for forming an external base layer in a region sandwiched between the third insulating film left on the side wall of the second insulating film and the mask material film; ,
After removing the mask material film, a step of selectively embedding a second conductor film that will become a part of the base electrode in the first opening, and burying the second conductor film and the oxidation-resistant film. Etching the first to third insulating films in the internal base formation region as a mask to form a second opening around the emitter formation region, implanting oxygen ions into the second opening region, and applying heat treatment. At the same time, forming an insulating film made of silicon dioxide, and forming a thermal oxide film on the surface of the film made of the first and second conductor films, impurities doped in advance in the second conductor film are added. forming an external base layer of a second conductivity type by diffusing into the collector layer; removing the oxidation-resistant film to form a third opening for forming an internal base; A step of doping the wafer surface in the opening region with an impurity to form an internal base layer of a second conductivity type, and exposing the wafer surface in the third opening region where the internal base layer is formed, forming a part of the emitter electrode. A bipolar transistor comprising the steps of: depositing a third conductor film, and diffusing impurities into the wafer through the third conductor film to form an emitter layer of a first conductivity type. manufacturing method.