JPH01101072A - Image synthesizing device - Google Patents

Abstract

PURPOSE:To synthesize two images without damaging them by displaying two kinds of image data to be synthesized alternately at every other line. CONSTITUTION:A VTR signal 1 is inputted to a write control circuit A13 and is converted to a digital RGB signal and is written in a RAM part 26 of a RAM incorporating a shifter. A personal computer RGB signal 12 is written in a RAM part 28 of a RAM incorporating a shifter by a write control circuit B. When a request signal 33 of read data is inputted, data of pertinent lines is transferred to shifters 27 and 29 from RAM parts 26 and 28. Transferred data is read out by serial clocks, which a read control circuit 32 alternately outputs to shifters 27 and 29 for respective lines, and is displayed on a display device 34. Thus, two input images are synthesized and displayed without a changeover switch.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to image synthesis and display, and particularly to an image synthesis apparatus suitable for synthesis of high-definition video signals.

[Conventional technology]

As described in Japanese Unexamined Patent Publication No. 60-12888, conventional image synthesis devices selectively combine the first video signal and the second video signal by detecting the black portion of the second video signal. A single image was synthesized by extracting the images.

This conventional image synthesis apparatus will be explained below with reference to FIGS. 2 and 3.

FIG. 2 shows a block diagram of a conventional image synthesis device. In FIG. The second video signal is shown. However, it is assumed that the vertical synchronization and horizontal synchronization of the first video signal 1 and the second video signal 2 are completely the same. 4 indicates the video signal 2 of WX2. 6 is based on the output of the black detection circuit 4.

1st. Or a switch circuit that switches the second video signal,
7 is an output switched by the switch circuit 6 and represents a composite video signal.

In addition, Fig. 3 is a diagram showing the operation of Fig. 2, and in Fig. 1, the second
Items K with the same content as in the figure have been assigned the same number.

In the conventional image synthesis device, a black detection circuit 4 detects the black part of the second video signal, and a switch circuit 6 detects the first video signal 1 and the second video signal 2 depending on the output of the black detection circuit 4.
When the black display part of the second video signal is switched and outputted, the first video signal is inserted into the black display part of the second video signal and a composite video signal 7 is generated.
This is what is output as. The black detection circuit 4 compares the brightness level of the second video signal with a reference voltage, and when the brightness level of the second video signal 2 is lower than the reference voltage, the second video signal 2 is in a black display period, that is, a non-black display period. It is determined that it is the display period and outputs a switching signal to connect the switch to the terminal 6a side pressure. On the other hand, when the brightness level of the second video signal 2 is higher than the reference voltage, the switch 6 is connected to the terminal 6.
Outputs a switching signal to switch to .

Therefore, the output terminal 64 of the switch 6 receives the second signal only during the period when the luminance level of the second video signal 2 is higher than the reference voltage.
In other cases, the first video signal 1 is output. Figure 3 shows the display pattern. The second video signal 2 is an image showing an annular region as shown in the region 2h, and the luminance level is higher than the reference voltage only during the period of the region 2h.Therefore, the output of the black detection circuit 4 is The second video signal is outputted from the switch 6 only during this period, and the second video signal is displayed on the area 2α where the first video signal is displayed on the image. Area 2b is displayed overlapping 5
It looks like

[Problem that the invention seeks to solve]

The above-mentioned conventional technology does not take into account the high-speed response of the changeover switch in single image synthesis.1For example, if the second video signal is a personal computer that provides a high-definition image,
The switching speed and transmission performance require a very wide band. There was a problem. Also, the second image shows the first
When decorating an image, no consideration was given to the fact that the display part of the second image would hide the display of the first image, thereby impairing the display of the first image.

It is an object of the present invention to realize image synthesis without a high-performance changeover switch, and to synthesize two images without damaging each other's images.

[Means for solving problems]

The above purpose is to combine two types of image data.

This is achieved by alternately displaying every other line.

[Effect]

The display means displays two types of image data every l line. As a result, the two types of images appear to be visually superimposed, so that the system operates as an image compositing device.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1, 4, 5, and the sixth factor. The first factor is a block diagram of an embodiment of the present invention. In Q, 11 is an example of first input image data, which is a VTR signal, 12 is an example of second input image data, which is a computer RGB signal, and 13 is a written Control circuits A and 14 are write control circuits B.

26, 27, 28, and 29 are thick built-in RAMs, with 26.degree. 28 being a RAM section and 27.29 being a thick section.

The operation of this RAM will be described later. 32 is a read control circuit, 33 is a read data request signal, and 34 is a display.

Figure 4 shows thick built-in R of 26, 27, 28, and 29.
The operation of AM is explained, and in Figure 1, 43 is the write data, 45 is the transfer row data, 46 is the RAS waveform of the memory control signal, 47 is the π1 (transfer signal) waveform, and 48 is the WE
(Write signal) waveform. Figure 5 shows the chic built-in RA
In the timing chart of the peripheral operation of the chic part of M, 61 in figure 1 is the serial clock of 27 manual power of the chic, and 62 is the serial clock of 29 manual power of the shifter.

63 and 64 are respective output data.

FIG. 6 shows a display example, and 51 and 54 in the figure are VTR images displaying video A. 52 and 55 are images B, which are computer images. 53 and 56 are composite screen displays. The details of one embodiment of the present invention will be explained below with reference to FIG. The VTR signal 11 is input to the write control circuit A13, which has a KGB demodulation circuit and an A/D conversion circuit, and the VTR signal 11 is converted into a digital RGB signal. The converted signals are write-controlled and written one after another into the RAM section 26 of the thick built-in RAM (.Meanwhile, the personal computer RGB12 is written one after another into the RAM section 28 of the shifter built-in RAM by the write control circuit B (here). The operation of the thick built-in RAM will be briefly explained using Fig. 5. In Fig. 5, in the cycle (1), the RAS
The write data 43 is written to the address specified by , CAS. And in cycle (11),
A row address is specified by the RAS waveform 46, and when the same cycle KDT waveform 47 is input, the specified row data 45 is transferred to the shifter 42.

The shifter 42 outputs this data serially by inputting a serial clock.

As described above, this thick built-in RAM can be randomly accessed like a normal RAM, and at the same time can input and output data for one row completely asynchronously through two ports in one transfer cycle. This transfer cycle is written to the control circuit A1.
3 and B14 is a read data request signal 33.

When the request signal 33 is input to the write control circuits A13 and B14, the data of the corresponding line is transferred to the RAM section 26.
, 28 to shifters 27 and 29. The transferred data is read out by the read control circuit 32 for each line by a serial clock that is alternately outputted by the busy shifter 27 and the shifter 291C. The read data is converted into one display data by the read control circuit 32 and displayed on the display 34. The read control circuit 32 outputs a request signal 33 when it has finished reading data from both the shifter 27 and the shifter 29. A timing chart of the above-described sick operation is shown in FIG. When the serial clock 61 is input to the shifter 27, the row data 63 that has been transferred is read out one after another. Similarly, when the serial clock 62 is input to the shifter 29, the row data 64 that has been transferred is read out one after another. When the serial clocks 61 and 62 are not input, the output has a high impedance width, allowing data to be sent out alternately. When the row data of the shifters 27 and 29 have been read out, a read request signal 33 of a transfer request is sent from the read control circuit 32 to the write control circuits A13 and B14.
is output to. Thereafter, by repeating this process, data on every other line is read out alternately and converted into analog values, and two picture frames are alternately displayed on the display screen of the display 34 on every other line. The 61st 'ffl shows an example of the display. For ease of understanding, the synthesis of vh6 figure) assumes a very rough stroke:f line.

The composite image 53 consists of the image fiA 51 and the image B 52 in one line.
You can see that the images are displayed alternately. The composition shown in (A) is an application of this technique to makeup stains and blemishes, resulting in a scanned image with such high definition that the scanning lines cannot be discerned.

By combining the face photo of video A54 with the makeup and wig drawn on the computer of video 9 B55.

In the composite image 56, you can see a face photo with makeup and hairstyle that are not actually applied. In this case, unlike conventional image compositing, it is possible to decorate with the second image RK while retaining the texture of the area to be made up in the face photo, which is the filler image.

As described above, according to this embodiment, two input images can be displayed in a composite manner without a changeover switch, and the composite display does not damage the original images.

〔Effect of the invention〕

According to the present invention, no changeover switch is required to synthesize one image, and two images to be synthesized can be superimposed on each other without covering the other. Therefore, both images can be viewed in the composite part. There is an effect.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a block diagram of a conventional example of an image synthesis device, Fig. 3 is an explanatory diagram of the operation of Fig. 2, and Fig. 4 is adopted in this embodiment. Chic built-in R
The figure which shows the structure and operation|movement of AM. FIG. 5 is a timing chart showing a part of the operation of the present invention, and FIG. 6 is an explanatory diagram showing the effects of the present invention. 13...Write control circuit A. 14...Write control circuit B. 26, 28... RAM section of thick built-in RAM, 27
, 29...Sick section of built-in RAM. 32...Reading control circuit. 82nd side 3rd figure 4- concave (a,)

Claims (1)

[Claims] 1. In an image synthesizing device that synthesizes a first image and a second image, a first storage means for storing first image data, and a first storage means for writing the first image data into the first storage means.
a second storage means for storing second image data; a second write control means for writing second image data into the second storage means; 1. An image synthesizing apparatus comprising: a display means for alternately reading and displaying first and second image data stored in the second storage means for each scanning line.