JP7617003B2 - 記憶装置 - Google Patents

記憶装置 Download PDF

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Publication number
JP7617003B2
JP7617003B2 JP2021538508A JP2021538508A JP7617003B2 JP 7617003 B2 JP7617003 B2 JP 7617003B2 JP 2021538508 A JP2021538508 A JP 2021538508A JP 2021538508 A JP2021538508 A JP 2021538508A JP 7617003 B2 JP7617003 B2 JP 7617003B2
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Japan
Prior art keywords
conductor
semiconductor
insulator
transistor
film
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JP2021538508A
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Japanese (ja)
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JPWO2021024071A1 (https=
JPWO2021024071A5 (https=
Inventor
舜平 山崎
肇 木村
隆徳 松嵜
達也 大貫
佑樹 岡本
秀貴 魚地
悟 岡本
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Publication of JPWO2021024071A1 publication Critical patent/JPWO2021024071A1/ja
Publication of JPWO2021024071A5 publication Critical patent/JPWO2021024071A5/ja
Priority to JP2025001916A priority Critical patent/JP7829073B2/ja
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/031—Manufacture or treatment of data-storage electrodes
    • H10D64/035—Manufacture or treatment of data-storage electrodes comprising conductor-insulator-conductor-insulator-semiconductor structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5671—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge trapping in an insulator
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/50—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/70—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6728—Vertical TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/031—Manufacture or treatment of data-storage electrodes
    • H10D64/037—Manufacture or treatment of data-storage electrodes comprising charge-trapping insulators
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/08—Manufacture or treatment characterised by using material-based technologies using combinations of technologies, e.g. using both Si and SiC technologies or using both Si and Group III-V technologies

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
JP2021538508A 2019-08-02 2020-07-22 記憶装置 Active JP7617003B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2025001916A JP7829073B2 (ja) 2019-08-02 2025-01-06 記憶装置

Applications Claiming Priority (9)

Application Number Priority Date Filing Date Title
JP2019143203 2019-08-02
JP2019143203 2019-08-02
JP2019152617 2019-08-23
JP2019152617 2019-08-23
JP2019220338 2019-12-05
JP2019220338 2019-12-05
JP2019230220 2019-12-20
JP2019230220 2019-12-20
PCT/IB2020/056864 WO2021024071A1 (ja) 2019-08-02 2020-07-22 記憶装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2025001916A Division JP7829073B2 (ja) 2019-08-02 2025-01-06 記憶装置

Publications (3)

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JPWO2021024071A1 JPWO2021024071A1 (https=) 2021-02-11
JPWO2021024071A5 JPWO2021024071A5 (https=) 2023-07-13
JP7617003B2 true JP7617003B2 (ja) 2025-01-17

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JP2025001916A Active JP7829073B2 (ja) 2019-08-02 2025-01-06 記憶装置

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US (2) US12347491B2 (https=)
JP (2) JP7617003B2 (https=)
WO (1) WO2021024071A1 (https=)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116368602A (zh) 2020-10-02 2023-06-30 株式会社半导体能源研究所 半导体装置
JP2022146030A (ja) * 2021-03-22 2022-10-05 キオクシア株式会社 半導体記憶装置及びその製造方法
KR20240093546A (ko) 2021-10-27 2024-06-24 가부시키가이샤 한도오따이 에네루기 켄큐쇼 표시 장치
JP2024001641A (ja) * 2022-06-22 2024-01-10 キオクシア株式会社 半導体装置及びその製造方法
KR20240032551A (ko) * 2022-09-02 2024-03-12 삼성전자주식회사 수직구조 트랜지스터 및 제조방법
CN119947080B (zh) * 2023-11-02 2026-04-03 北京超弦存储器研究院 一种半导体器件及其制造方法、电子设备

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016063027A (ja) 2014-09-17 2016-04-25 株式会社東芝 不揮発性半導体記憶装置及びその製造方法
JP2018157208A (ja) 2017-03-16 2018-10-04 東芝メモリ株式会社 半導体メモリ
JP2018207039A (ja) 2017-06-08 2018-12-27 株式会社半導体エネルギー研究所 半導体装置、記憶装置、及び電子機器
JP2018207038A (ja) 2017-06-08 2018-12-27 株式会社半導体エネルギー研究所 半導体装置、記憶装置、及び電子機器
JP2019008862A (ja) 2017-06-26 2019-01-17 株式会社半導体エネルギー研究所 半導体装置、電子機器

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6156620A (en) 1998-07-22 2000-12-05 Lsi Logic Corporation Isolation trench in semiconductor substrate with nitrogen-containing barrier region, and process for forming same
US20090282763A1 (en) 2008-05-19 2009-11-19 Samuel Joseph Ferguson Structural building component having a decorative overmolding, apparatus for fabricating such an article and its method of manufacture
KR101698193B1 (ko) 2009-09-15 2017-01-19 삼성전자주식회사 3차원 반도체 메모리 장치 및 그 제조 방법
US8802493B2 (en) 2011-09-13 2014-08-12 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of oxide semiconductor device
US20160079265A1 (en) * 2014-09-12 2016-03-17 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device and method of manufacturing the same
US9711522B2 (en) 2014-10-03 2017-07-18 Sandisk Technologies Llc Memory hole structure in three dimensional memory
US9634097B2 (en) 2014-11-25 2017-04-25 Sandisk Technologies Llc 3D NAND with oxide semiconductor channel
JP6343256B2 (ja) * 2015-05-29 2018-06-13 東芝メモリ株式会社 半導体装置及びその製造方法
JP6400536B2 (ja) 2015-08-04 2018-10-03 東芝メモリ株式会社 半導体記憶装置
US20170062456A1 (en) 2015-08-31 2017-03-02 Cypress Semiconductor Corporation Vertical division of three-dimensional memory device
US10497712B2 (en) * 2017-03-16 2019-12-03 Toshiba Memory Corporation Semiconductor memory
US10312239B2 (en) 2017-03-16 2019-06-04 Toshiba Memory Corporation Semiconductor memory including semiconductor oxie
US10553601B2 (en) * 2017-03-16 2020-02-04 Toshiba Memory Corporation Semiconductor memory including semiconductor oxide
US10593693B2 (en) 2017-06-16 2020-03-17 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing semiconductor device
US10665604B2 (en) * 2017-07-21 2020-05-26 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, semiconductor wafer, memory device, and electronic device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016063027A (ja) 2014-09-17 2016-04-25 株式会社東芝 不揮発性半導体記憶装置及びその製造方法
JP2018157208A (ja) 2017-03-16 2018-10-04 東芝メモリ株式会社 半導体メモリ
JP2018207039A (ja) 2017-06-08 2018-12-27 株式会社半導体エネルギー研究所 半導体装置、記憶装置、及び電子機器
JP2018207038A (ja) 2017-06-08 2018-12-27 株式会社半導体エネルギー研究所 半導体装置、記憶装置、及び電子機器
JP2019008862A (ja) 2017-06-26 2019-01-17 株式会社半導体エネルギー研究所 半導体装置、電子機器

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Publication number Publication date
JPWO2021024071A1 (https=) 2021-02-11
US12347491B2 (en) 2025-07-01
WO2021024071A1 (ja) 2021-02-11
US20250292834A1 (en) 2025-09-18
US20220262438A1 (en) 2022-08-18
JP2025061043A (ja) 2025-04-10
JP7829073B2 (ja) 2026-03-12

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