JP7606101B2 - 半導体記憶装置 - Google Patents

半導体記憶装置 Download PDF

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Publication number
JP7606101B2
JP7606101B2 JP2021524796A JP2021524796A JP7606101B2 JP 7606101 B2 JP7606101 B2 JP 7606101B2 JP 2021524796 A JP2021524796 A JP 2021524796A JP 2021524796 A JP2021524796 A JP 2021524796A JP 7606101 B2 JP7606101 B2 JP 7606101B2
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Japan
Prior art keywords
transistors
transistor
node
port sram
cell
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Active
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JP2021524796A
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English (en)
Japanese (ja)
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JPWO2020246344A1 (https=
Inventor
真一 森脇
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Socionext Inc
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Socionext Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • H10B10/125—Static random access memory [SRAM] devices comprising a MOSFET load element the MOSFET being a thin film transistor [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/43—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6735—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes having gates fully surrounding the channels, e.g. gate-all-around
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
    • H10D62/118—Nanostructure semiconductor bodies
    • H10D62/119—Nanowire, nanosheet or nanotube semiconductor bodies
    • H10D62/121—Nanowire, nanosheet or nanotube semiconductor bodies oriented parallel to substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/82—Heterojunctions
    • H10D62/822—Heterojunctions comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00—Three-dimensional [3D] integrated devices

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  • Semiconductor Memories (AREA)
  • Static Random-Access Memory (AREA)
JP2021524796A 2019-06-03 2020-05-27 半導体記憶装置 Active JP7606101B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2019103722 2019-06-03
JP2019103722 2019-06-03
PCT/JP2020/020975 WO2020246344A1 (ja) 2019-06-03 2020-05-27 半導体記憶装置

Publications (2)

Publication Number Publication Date
JPWO2020246344A1 JPWO2020246344A1 (https=) 2020-12-10
JP7606101B2 true JP7606101B2 (ja) 2024-12-25

Family

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JP2021524796A Active JP7606101B2 (ja) 2019-06-03 2020-05-27 半導体記憶装置

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Country Link
US (1) US12127388B2 (https=)
JP (1) JP7606101B2 (https=)
WO (1) WO2020246344A1 (https=)

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JP7590655B2 (ja) * 2019-06-21 2024-11-27 株式会社ソシオネクスト 半導体記憶装置
US11114153B2 (en) * 2019-12-30 2021-09-07 Taiwan Semiconductor Manufacturing Co., Ltd. SRAM devices with reduced coupling capacitance
US12046652B2 (en) * 2020-06-25 2024-07-23 Intel Corporation Plug and recess process for dual metal gate on stacked nanoribbon devices
US11488969B1 (en) * 2021-04-08 2022-11-01 Taiwan Semiconductor Manufacturing Company, Ltd. Two-port SRAM cells with asymmetric M1 metalization
US12349458B2 (en) * 2022-03-22 2025-07-01 International Business Machines Corporation Staggered stacked circuits with increased effective width
EP4621783A1 (en) * 2024-03-22 2025-09-24 INTEL Corporation Balanced static random-access memory (sram)
WO2025234291A1 (ja) * 2024-05-08 2025-11-13 株式会社ソシオネクスト 半導体記憶装置
WO2025243827A1 (ja) * 2024-05-21 2025-11-27 株式会社ソシオネクスト 半導体記憶装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009295975A (ja) 2008-06-02 2009-12-17 Commiss Energ Atom いくつかのレベルのところに集積された、しきい値電圧ｖｔが動的に調整可能なトランジスタを有するｓｒａｍメモリセル
JP2013143536A (ja) 2012-01-12 2013-07-22 Toshiba Corp 半導体装置及びその製造方法
WO2014184933A1 (ja) 2013-05-16 2014-11-20 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド Ｓｇｔを有する半導体装置の製造方法
WO2014185085A1 (ja) 2013-05-14 2014-11-20 株式会社 東芝 半導体記憶装置

Family Cites Families (17)

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Publication number Priority date Publication date Assignee Title
JP2665644B2 (ja) 1992-08-11 1997-10-22 三菱電機株式会社 半導体記憶装置
KR20150058597A (ko) * 2013-11-18 2015-05-29 삼성전자주식회사 반도체 장치 및 그 제조 방법
US9362292B1 (en) * 2015-04-17 2016-06-07 Taiwan Semiconductor Manufacturing Company, Ltd. Two-port SRAM cell structure for vertical devices
US10211206B1 (en) * 2017-11-01 2019-02-19 Globalfoundries Inc. Two-port vertical SRAM circuit structure and method for producing the same
KR20250070116A (ko) * 2017-11-30 2025-05-20 인텔 코포레이션 진보된 집적 회로 구조체 제조를 위한 핀 패터닝
JPWO2019159739A1 (ja) * 2018-02-15 2021-01-28 株式会社ソシオネクスト 半導体集積回路装置
US10707218B2 (en) * 2018-07-26 2020-07-07 Globalfoundries Inc. Two port SRAM cell using complementary nano-sheet/wire transistor devices
WO2020070830A1 (ja) * 2018-10-03 2020-04-09 株式会社ソシオネクスト 半導体記憶装置
US11145660B2 (en) * 2019-07-31 2021-10-12 Taiwan Semiconductor Manufacturing Co., Ltd. Dual-port SRAM cell structure
US12354650B2 (en) * 2019-12-09 2025-07-08 The University Of North Carolina At Charlotte Integrated circuits with single-functional-unit level integration of electronic and photonic elements
WO2021125094A1 (ja) * 2019-12-19 2021-06-24 株式会社ソシオネクスト 半導体記憶装置
US11282843B2 (en) * 2020-05-22 2022-03-22 Taiwan Semiconductor Manufacturing Co., Ltd. Memory device, SRAM cell, and manufacturing method thereof
US20230317148A1 (en) * 2022-03-31 2023-10-05 Intel Corporation Epitaxial layers of a transistor electrically coupled with a backside contact metal
US12444685B2 (en) * 2022-03-31 2025-10-14 Intel Corporation Backside electrical contact for PMOS epitaxial voltage supply
US12453071B2 (en) * 2022-04-26 2025-10-21 Qualcomm Incorporated Gate spacer structures for three-dimensional semiconductor devices
EP4293721A1 (en) * 2022-06-15 2023-12-20 Imec VZW Bit cell for sram
EP4293720A1 (en) * 2022-06-15 2023-12-20 Imec VZW Bit cell with isolating wall

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009295975A (ja) 2008-06-02 2009-12-17 Commiss Energ Atom いくつかのレベルのところに集積された、しきい値電圧ｖｔが動的に調整可能なトランジスタを有するｓｒａｍメモリセル
JP2013143536A (ja) 2012-01-12 2013-07-22 Toshiba Corp 半導体装置及びその製造方法
WO2014185085A1 (ja) 2013-05-14 2014-11-20 株式会社 東芝 半導体記憶装置
WO2014184933A1 (ja) 2013-05-16 2014-11-20 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド Ｓｇｔを有する半導体装置の製造方法

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US12127388B2 (en) 2024-10-22
US20220093613A1 (en) 2022-03-24
WO2020246344A1 (ja) 2020-12-10

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