JP7546559B2 - 非同期ａｓｉｃ - Google Patents

非同期ａｓｉｃ Download PDF

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Publication number
JP7546559B2
JP7546559B2 JP2021522076A JP2021522076A JP7546559B2 JP 7546559 B2 JP7546559 B2 JP 7546559B2 JP 2021522076 A JP2021522076 A JP 2021522076A JP 2021522076 A JP2021522076 A JP 2021522076A JP 7546559 B2 JP7546559 B2 JP 7546559B2
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JP
Japan
Prior art keywords
clock
data
circuitry
phase
candidates
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JP2021522076A
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English (en)
Japanese (ja)
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JPWO2020086760A5 (https=
JP2022505662A5 (https=
JP2022505662A (ja
Inventor
ニヴ マルガリット，
エヤル セラ，
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Magic Leap Inc
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Magic Leap Inc
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Publication date
Application filed by Magic Leap Inc filed Critical Magic Leap Inc
Publication of JP2022505662A publication Critical patent/JP2022505662A/ja
Priority to JP2022164507A priority Critical patent/JP7546635B2/ja
Publication of JP2022505662A5 publication Critical patent/JP2022505662A5/ja
Publication of JPWO2020086760A5 publication Critical patent/JPWO2020086760A5/ja
Priority to JP2024040843A priority patent/JP7565467B2/ja
Priority to JP2024153947A priority patent/JP7770497B2/ja
Application granted granted Critical
Publication of JP7546559B2 publication Critical patent/JP7546559B2/ja
Priority to JP2024178926A priority patent/JP7825684B2/ja
Priority to JP2026008500A priority patent/JP2026063316A/ja
Active legal-status Critical Current
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/06—Clock generators producing several clock signals
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066—Output synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1093—Input synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Manipulation Of Pulses (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Dram (AREA)
  • Information Transfer Systems (AREA)
JP2021522076A 2018-10-24 2019-10-23 非同期ａｓｉｃ Active JP7546559B2 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2022164507A JP7546635B2 (ja) 2018-10-24 2022-10-13 非同期ａｓｉｃ
JP2024040843A JP7565467B2 (ja) 2018-10-24 2024-03-15 非同期ａｓｉｃ
JP2024153947A JP7770497B2 (ja) 2018-10-24 2024-09-06 非同期ａｓｉｃ
JP2024178926A JP7825684B2 (ja) 2018-10-24 2024-10-11 非同期ａｓｉｃ
JP2026008500A JP2026063316A (ja) 2018-10-24 2026-01-21 非同期ａｓｉｃ

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201862750180P 2018-10-24 2018-10-24
US62/750,180 2018-10-24
PCT/US2019/057723 WO2020086760A2 (en) 2018-10-24 2019-10-23 Asynchronous asic

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2022164507A Division JP7546635B2 (ja) 2018-10-24 2022-10-13 非同期ａｓｉｃ

Publications (4)

Publication Number Publication Date
JP2022505662A JP2022505662A (ja) 2022-01-14
JPWO2020086760A5 JPWO2020086760A5 (https=) 2022-10-21
JP2022505662A5 JP2022505662A5 (https=) 2022-10-21
JP7546559B2 true JP7546559B2 (ja) 2024-09-06

Family

ID=70331255

Family Applications (6)

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JP2021522076A Active JP7546559B2 (ja) 2018-10-24 2019-10-23 非同期ａｓｉｃ
JP2022164507A Active JP7546635B2 (ja) 2018-10-24 2022-10-13 非同期ａｓｉｃ
JP2024040843A Active JP7565467B2 (ja) 2018-10-24 2024-03-15 非同期ａｓｉｃ
JP2024153947A Active JP7770497B2 (ja) 2018-10-24 2024-09-06 非同期ａｓｉｃ
JP2024178926A Active JP7825684B2 (ja) 2018-10-24 2024-10-11 非同期ａｓｉｃ
JP2026008500A Pending JP2026063316A (ja) 2018-10-24 2026-01-21 非同期ａｓｉｃ

Family Applications After (5)

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JP2022164507A Active JP7546635B2 (ja) 2018-10-24 2022-10-13 非同期ａｓｉｃ
JP2024040843A Active JP7565467B2 (ja) 2018-10-24 2024-03-15 非同期ａｓｉｃ
JP2024153947A Active JP7770497B2 (ja) 2018-10-24 2024-09-06 非同期ａｓｉｃ
JP2024178926A Active JP7825684B2 (ja) 2018-10-24 2024-10-11 非同期ａｓｉｃ
JP2026008500A Pending JP2026063316A (ja) 2018-10-24 2026-01-21 非同期ａｓｉｃ

Country Status (5)

Country Link
US (5) US11487316B2 (https=)
EP (2) EP3871062B1 (https=)
JP (6) JP7546559B2 (https=)
CN (2) CN113227935B (https=)
WO (1) WO2020086760A2 (https=)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
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CN113227935B (zh) 2018-10-24 2024-09-13 奇跃公司 异步asic
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US20240371422A1 (en) * 2021-09-10 2024-11-07 SK Hynix Inc. Data receiving circuit for chiplet based storage architectures
US12578753B2 (en) * 2023-01-27 2026-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. Clock aligning circuit and methods for operating the same

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Also Published As

Publication number Publication date
US11487316B2 (en) 2022-11-01
US12135580B2 (en) 2024-11-05
JP2024071432A (ja) 2024-05-24
WO2020086760A3 (en) 2020-07-30
CN119126919A (zh) 2024-12-13
US20230018203A1 (en) 2023-01-19
JP7546635B2 (ja) 2024-09-06
EP3871062B1 (en) 2025-11-26
US20210382520A1 (en) 2021-12-09
EP4672660A2 (en) 2025-12-31
CN113227935A (zh) 2021-08-06
JP2024178214A (ja) 2024-12-24
EP4672660A3 (en) 2026-04-08
CN113227935B (zh) 2024-09-13
EP3871062A2 (en) 2021-09-01
EP3871062A4 (en) 2021-12-29
US11747856B2 (en) 2023-09-05
US20230205257A1 (en) 2023-06-29
US11619965B2 (en) 2023-04-04
JP7825684B2 (ja) 2026-03-06
WO2020086760A2 (en) 2020-04-30
JP2026063316A (ja) 2026-04-10
JP2022183237A (ja) 2022-12-08
US20240370051A1 (en) 2024-11-07
JP7770497B2 (ja) 2025-11-14
US20230367361A1 (en) 2023-11-16
JP7565467B2 (ja) 2024-10-10
JP2022505662A (ja) 2022-01-14
JP2025004229A (ja) 2025-01-14

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