JP7525525B2 - 表示基板及びその駆動方法、表示装置 - Google Patents
表示基板及びその駆動方法、表示装置 Download PDFInfo
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- JP7525525B2 JP7525525B2 JP2021578106A JP2021578106A JP7525525B2 JP 7525525 B2 JP7525525 B2 JP 7525525B2 JP 2021578106 A JP2021578106 A JP 2021578106A JP 2021578106 A JP2021578106 A JP 2021578106A JP 7525525 B2 JP7525525 B2 JP 7525525B2
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Electroluminescent Light Sources (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Control Of El Displays (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Description
12 導線
13 ゲート駆動回路
14 データ駆動回路
20 基板
100 サブ画素
103 非表示領域
110 表示領域
130 ボンディング領域
131 ボンディング電極
132 配線
Claims (18)
- 表示基板であって、
ベース基板と、
前記ベース基板に位置し且つアレイで配列される複数のサブ画素と、を含み、
前記複数のサブ画素のそれぞれは画素回路を含み、前記画素回路は前記複数のサブ画素のそれぞれに対応する発光素子が発光するように駆動することに用いられ、
前記複数の画素回路のそれぞれは駆動サブ回路、データ書き込みサブ回路、補償サブ回路、記憶サブ回路及び第1リセットサブ回路を含み、
前記駆動サブ回路は制御端子、第1端子及び第2端子を含み、且つ前記発光素子に接続され且つ前記発光素子を流れる駆動電流を制御するように構成され、
前記データ書き込みサブ回路は前記駆動サブ回路の第1端子に接続され、且つ第1走査信号に応答してデータ信号を前記駆動サブ回路の第1端子に書き込むように構成され、
前記補償サブ回路は制御端子、第1端子及び第2端子を含み、前記補償サブ回路の制御端子は第2走査信号を受信するように構成され、前記補償サブ回路の第1端子及び第2端子はそれぞれ前記駆動サブ回路の制御端子及び第2端子に電気的に接続され、前記補償サブ回路は前記第2走査信号に応答して前記駆動サブ回路に対して閾値補償を行うように構成され、
前記記憶サブ回路は第1端子及び第2端子を含み、前記記憶サブ回路の第1端子は第1電源電圧を受信するように構成され、前記記憶サブ回路の第2端子は前記駆動サブ回路の制御端子に電気的に接続され、
前記第1リセットサブ回路は制御端子、第1端子及び第2端子を含み、前記第1リセットサブ回路の制御端子は第1リセット制御電圧を受信するように構成され、前記第1リセットサブ回路の第1端子は第1リセット電圧を受信するように構成され、前記第1リセットサブ回路の第2端子は前記発光素子に接続されるように構成され、
前記第1リセットサブ回路は前記発光素子を逆バイアスするように前記第1リセット制御電圧に応答して前記第1リセット電圧を前記発光素子に印加するように構成され、
前記複数のサブ画素は第1サブ画素を含み、前記表示基板は更に第1リセット電圧端子を含み、前記第1リセット電圧端子は前記第1サブ画素に前記第1リセット電圧を提供するために、前記第1サブ画素の第1リセットサブ回路の第1端子に接続されるように構成され、
前記複数の画素回路のそれぞれは更に第2リセットサブ回路を含み、
前記第2リセットサブ回路は前記駆動サブ回路の制御端子に接続され、且つ前記駆動サブ回路の制御端子をリセットするように、第2リセット制御電圧に応答して第2リセット電圧を前記駆動サブ回路の制御端子に印加するように構成され、
前記複数のサブ画素は第1方向及び第2方向に沿って複数の画素行及び複数の画素列として配列され、
前記表示基板は更に前記第1方向に沿って延伸する第1リセット電圧線を含み、前記第1リセット電圧線は前記サブ画素に前記第1リセット電圧を提供するようにそれぞれ前記第1リセット電圧端子及び前記第1リセットサブ回路の第1端子に電気的に接続され、
前記表示基板は更に前記第1方向に沿って延伸する第1リセット信号線を含み、
前記第1リセット信号線は前記第2リセット電圧を提供するように前記第2リセットサブ回路の制御端子に接続され、
前記第1リセット信号線は前記第1リセット電圧線の前記ベース基板に近い側に位置し、前記第1リセット信号線はドーピング半導体材料を含む、表示基板。 - 更に第2リセット電圧端子を含み、
前記第2リセット電圧端子は前記第2リセット電圧を提供するように前記第2リセットサブ回路に接続されるように構成され、
前記第2リセット電圧端子が出力した前記第2リセット電圧は前記第1リセット電圧端子が出力した前記第1リセット電圧より大きい、請求項1に記載の表示基板。 - 更に前記第2方向に沿って延伸する第2リセット信号線を含み、
前記第2リセット信号線は前記第1リセット電圧線の前記ベース基板から離れる側に位置し、且つ前記第1リセット信号線に電気的に接続される、請求項1に記載の表示基板。 - 前記複数の画素回路のそれぞれは更に第1接続電極を含み、
前記第1接続電極は前記第1リセット電圧線の前記ベース基板から離れる側に位置し、前記第1接続電極はそれぞれ前記第1リセットサブ回路の第1端子及び第1リセット電圧線に電気的に接続される、請求項1~3のいずれか一項に記載の表示基板。 - 前記記憶サブ回路は、第1コンデンサ電極及び第2コンデンサ電極を含む記憶コンデンサを含み、
前記第1コンデンサ電極は前記第1リセット電圧線と同じ層に絶縁設置され、前記第2コンデンサ電極は前記第1コンデンサ電極が前記ベース基板に近い側に位置する、請求項4に記載の表示基板。 - 前記複数の画素回路のそれぞれは更に第2接続電極を含み、
前記第2接続電極は前記第1接続電極と同じ層に絶縁設置され、前記第2接続電極はそれぞれ前記第2コンデンサ電極及び前記補償サブ回路の第1端子に電気的に接続される、請求項5に記載の表示基板。 - 前記第1コンデンサ電極は開口を含み、前記第2接続電極は前記第1コンデンサ電極から絶縁され、且つ前記開口によって前記第2コンデンサ電極に電気的に接続される、請求項6に記載の表示基板。
- 前記複数の画素回路のそれぞれは更に第3接続電極を含み、
前記第3接続電極は前記第1接続電極と同じ層に絶縁設置され、前記第3接続電極は第1接続端子及び第2接続端子を含み、前記第1接続端子は前記第1リセットサブ回路の第2端子に電気的に接続され、前記第2接続端子は前記発光素子に接続されることに用いられる、請求項4~7のいずれか一項に記載の表示基板。 - 前記複数の画素回路のそれぞれは更に発光制御サブ回路を含み、
前記発光制御サブ回路は制御端子、第1端子及び第2端子を含み、前記発光制御サブ回路の第1端子は前記駆動サブ回路の第2端子に接続され、前記発光制御サブ回路の第2端子は前記発光素子に接続されることに用いられる、請求項8に記載の表示基板。 - 前記第3接続電極は更に第3接続端子を含み、前記第3接続端子は前記発光制御サブ回路の第2端子に電気的に接続されることで、前記発光制御サブ回路の第2端子を前記発光素子に接続する、請求項9に記載の表示基板。
- 前記第3接続電極はU型構造であり、
前記第1接続端子及び前記第2接続端子はそれぞれ前記U型構造の2つの端点に位置し、前記第3接続端子は前記U型構造の前記第2接続端子に近い曲がり角に位置する、請求項10に記載の表示基板。 - 前記複数のサブ画素は更に第2サブ画素を含み、前記第1サブ画素及び前記第2サブ画素は異なる色を発する発光素子に対応し、
前記表示基板は更に第3リセット電圧端子を含み、前記第3リセット電圧端子は前記第2サブ画素に前記第1リセット電圧を提供するように前記第2サブ画素の第1リセットサブ回路の第1端子に接続されるように構成され、
前記第1リセット電圧端子が出力した第1リセット電圧と前記第3リセット電圧端子が出力した第1リセット電圧とは異なる、請求項1~11のいずれか一項に記載の表示基板。 - 前記第1リセット電圧端子が出力した第1リセット電圧は前記第3リセット電圧端子が出力した第1リセット電圧より小さい、請求項12に記載の表示基板。
- 前記複数のサブ画素は更に第3サブ画素を含み、前記第1サブ画素、前記第2サブ画素及び前記第3サブ画素はそれぞれ青色発光素子、赤色発光素子及び緑色発光素子に対応し、
前記第3リセット電圧端子は前記第3サブ画素に前記第1リセット電圧を提供するように更に前記第3サブ画素の第1リセットサブ回路の第1端子に接続される、請求項12又は13に記載の表示基板。 - 更に前記第1方向に沿って延伸する第2リセット電圧線を含み、
前記第1サブ画素、前記第2サブ画素及び前記第3サブ画素は同じ画素行にあり、
前記第1リセット電圧線は前記第1サブ画素の第1リセットサブ回路の第1端子と前記第1リセット電圧端子とを電気的に接続し、前記第2リセット電圧線は前記第2サブ画素の第1リセットサブ回路の第1端子及び前記第3サブ画素の第1リセットサブ回路の第1端子と前記第3リセット電圧端子とを電気的に接続する、請求項14に記載の表示基板。 - 駆動方法であって、請求項1~15のいずれか一項に記載の表示基板に用いられ、リセット段階と、発光段階とを含み、
前記リセット段階は、前記第1リセットサブ回路をオンにするように、前記第1リセット制御電圧及び前記第1リセット電圧を入力し、前記発光素子を逆バイアスするように、前記第1リセット電圧を前記発光素子に印加することを含み、
前記発光段階は、前記駆動サブ回路をオンにして、前記駆動電流を前記発光素子に印加することで、前記発光素子に発光させることを含む駆動方法。 - 更にデータ書き込み及び補償段階を含み、
前記データ書き込み及び補償段階は、前記データ書き込みサブ回路、前記駆動サブ回路及び前記補償サブ回路をオンにするように、前記第1走査信号、前記第2走査信号及び前記データ信号を入力し、それにより、前記データ信号が前記駆動サブ回路に書き込まれ、前記補償サブ回路が前記データ信号を記憶し、且つ前記補償サブ回路が前記駆動サブ回路を補償することを含む、請求項16に記載の駆動方法。 - 表示装置であって、
請求項1~15のいずれか一項に記載の表示基板及び複数の発光素子を含み、
前記複数の発光素子は前記複数のサブ画素と1対1で対応し、前記複数の発光素子のそれぞれは第1電極及び第2電極を含み、前記各発光素子の第1電極は対応するサブ画素の第1リセットサブ回路の第2端子に接続される、表示装置。
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